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IDT7007S15J Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7007S15J Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 21 page 1 JUNE 1999 DSC 2940/8 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A14L A0L 2940 drw 01 I/O0L- I/O7L CEL OEL R/ WL SEML INTL M/ S BUSYR I/O0R-I/O7R A14R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER R/ WR 15 15 HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM Features x True Dual-Ported memory cells which allow simultaneous reads of the same memory location x High-speed access Military:25/35/55ns(max.) Industrial: 55ns (max.) Commercial:15/20/25/35/55ns(max.) x Low-power operation IDT7007S Active: 850mW (typ.) Standby: 5mW (typ.) IDT7007L Active: 850mW (typ.) Standby: 1mW (typ.) x IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device x M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave x Interrupt Flag x On-chip port arbitration logic x Full on-chip hardware support of semaphore signaling between ports x Fully asynchronous operation from either port x TTL-compatible, single 5V (±10%) power supply x Available in 68-pin PGA and PLCC and a 80-pin TQFP x Industrial temperature range (40°C to +85°C) is available for selected speeds NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. Functional Block Diagram IDT7007S/L |
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