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IDT7016L12GB Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT7016L12GB Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 20 page 6.13 10 IDT7016S/L HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/ W W W W W CONTROLLED TIMING(1,5,8) R/ W tWC tHZ tAW tWR tAS tWP DATAOUT (2) tWZ tDW tDH tOW OE ADDRESS DATAIN CE or SEM (6) (4) (4) (3) 3190 drw 09 (7) (9) (7) NOTES: 1. R/ W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a Low CE and a Low R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured +/-200mV from steady state with the Output Test load (Figure 2). 8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 3190 drw 10 tWC tAS tWR tDW tDH ADDRESS DATAIN CE or SEM R/ W tAW tEW (3) (2) (6) (9) TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CE CE CE CE CONTROLLED TIMING(1,5) |
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