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IDT71V321S55PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT71V321S55PF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 14 page 6.42 IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 10 Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) Timing Waveform of BUSY Arbritration Controlled by Address Match Timing(1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only). NOTES: 1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. tWB is for the slave version (71V421). 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A". Timing Waveform of Write with BUSY(4) BUSY"B" 3026 drw 11 R/ W"A" tWP tWH tWB R/W"B" (2) (1) (3) , tAPS (2) ADDR "A" AND "B" ADDRESSES MATCH tBAC tBDC CE"B" CE"A" BUSY"A" 3026 drw 12 BUSY"B" ADDRESSES DO NOT MATCH ADDRESSES MATCH tAPS ADDR"A" ADDR"B" tRC OR tWC 3026 drw 13 (2) tBAA tBDA |
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