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IDT7223611L20PQF Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT7223611L20PQF Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 20 page  IDT723611 CMOS SyncFIFO ™ 64 x 36 COMMERCIAL TEMPERATURE RANGES 9 SIGNAL DESCRIPTION RESET ( RST RST) The IDT723611 is reset by taking the reset ( RST) input LOW for at least four port-A clock (CLKA) and four port-B clock (CLKB) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of the FIFO and forces the full- flag ( FF) LOW, the empty flag (EF) LOW, the almost-empty flag ( AE) LOW, and the almost-full flag (AF) HIGH. A reset also forces the mailbox flags ( MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH transitions of CLKA. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the almost-full and almost-empty offset register (X) with the value selected by the flag select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1. FIFO WRITE/READ OPERATION The state of the port-A data (A0-A35) outputs is controlled by the port-A chip select ( CSA) and the port-A write/read select (W/ RA). The A0-A35 outputs are in the high-imped- ance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to- HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FF is HIGH (see Table 2). The port-B control signals are identical to those of port A. The state of the port-B data (B0-B35) outputs is controlled by the port-B chip select ( CSB) and the port-B write/read select (W/ RB). The B0-B35 outputs are in the high-impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are active when both CSB and W/RB are LOW. Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and EF is HIGH (see Table 3). Almost-Full and Almost-Empty Flag FS1 FS0 RST RST Offset Register (X) 16 H H ↑ 12 H L ↑ 8L H ↑ 4L L ↑ Table 1. Flag Programming CSA CSA W/ RRA ENA MBA CLKA A0-A35 Outputs Port Functions H X X X X In High-Impedance State None L H L X X In High-Impedance State None LH HL ↑ In High-Impedance State FIFO Write LH H H ↑ In High-Impedance State Mail1 Write L L L L X Active, Mail2 Register None LL H L ↑ Active, Mail2 Register None L L L H X Active, Mail2 Register None LL H H ↑ Active, Mail2 Register Mail2 Read (set MBF2 HIGH) Table 2. Port-A Enable Function Table CSB CSB W/ RRB ENB MBB CLKB B0-B35 Outputs Port Functions H X X X X In High-Impedance State None L H L X X In High-Impedance State None LH HL ↑ In High-Impedance State None LH H H ↑ In High-Impedance State Mail2 Write L L L L X Active, FIFO Output Register None LL H L ↑ Active, FIFO Output Register FIFO Read L L L H X Active, Mail1 Register None LL H H ↑ Active, Mail1 Register Mail1 Read (set MBF1 HIGH) Table 3. Port-B Enable Function Table |
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