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IDT7024L17PFB Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT7024L17PFB
Description  HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7024L17PFB Datasheet(HTML) 1 Page - Integrated Device Technology

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Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2740/6
IDT7024S/L
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
more than one device
•M/
S = H for BUSY output flag on Master
M/
S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Devices are capable of withstanding greater than 2001V
electrostatic discharge.
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (
±10%) power supply
• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
• Industrial temperature range (–40
°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE):
BUSY
is input.
2.
BUSY outputs
and
INT outputs
are non-tri-stated
push-pull.
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.15
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
WL
BUSYL
A11L
A0L
2740 drw 01
UBL
LBL
CEL
OEL
I/O8L-I/O 15L
I/O0L-I/O 7L
CEL
OEL
R/
WL
SEML
INTL
M/
S
R/
WR
BUSYR
UBR
LBR
CER
OER
I/O8R-I/O 15R
I/O0R-I/O 7R
A11R
A0R
R/
WR
SEMR
INTR
CER
OER
(2)
(1,2)
(1,2)
(2)
12
12


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