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IDT7130LA25J Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT7130LA25J Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 14 page IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.01 4 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%) 7130X20 (2) 7130X25(3) 7130X35 7130X55 7130X100 7140X25 (3) 7140X35 7140X55 7140X100 Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit ICC Dynamic Operating CEL and CER = VIL, MIL. SA — — 110 280 110 230 110 190 110 190 mA Current (Both Ports Outputs open, LA — — 110 220 110 170 110 140 110 140 Active) f = fMAX (4) COM'L. SA 110 250 110 220 110 165 110 155 110 155 LA 110 200 110 170 110 120 110 110 110 110 ISB1 Standby Current CEL and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA (Both Ports - TTL f = fMAX (4) LA — — 30 60 25 60 20 45 20 45 Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55 LA 30 45 30 45 25 45 20 35 20 35 ISB2 Standby Current CE"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA (One Port - TTL CE"B" = VIH (7) LA — — 65 125 50 115 40 90 40 90 Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110 Open, f = fMAX (4) LA 65 125 65 115 50 90 40 75 40 75 ISB3 Full Standby Current CEL and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA (Both Ports - All CER > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10 CMOS Level Inputs VIN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15 VIN < 0.2V,f = 0 (5) LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4 ISB4 Full Standby Current CE"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA (One Port - All CE"B" > VCC -0.2V(7) LA — — 60 115 45 105 40 85 40 80 CMOS Level Inputs) VIN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95 VIN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70 Active Port Outputs Open, f = fMAX (4) NOTES: 2689 tbl 06 1. 'X' in part numbers indicates power rating (SA or LA). 2. Com'l Only, 0 °C to +70°C temperature range. PLCC and TQFP packages. 3. Not available in DIP packages. 4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 6. Vcc = 5V, TA=+25 °C for Typ and is not production tested. Vcc DC = 100 mA (Typ.) 7. Port "A" may be either left or right port. Port "B" is opposite from port "A". Symbol Parameter Min. Typ. (1) Max. Unit VDR VCC for Data Retention 2.0 — — V ICCDR Data Retention Current — 100 4000 µA — 100 1500 µA tCDR Chip Deselect to Data 0 — — ns Retention Time tR Operation Recovery tRC —— ns Time DATA RETENTION CHARACTERISTICS (LA Version Only) lDT7130LA/IDT7140LA Mil. Com’l. VCC = 2.0V, CE > VCC -0.2V VIN > VCC -0.2V or VIN < 0.2V (3) (3) Test Conditions 2689 tbl 07 (2) NOTES: 1. VCC = 2V, TA = +25 °C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested. |
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