MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1997

©1997 Integrated Device Technology, Inc

DSC-3037/7

1

Integrated Device Technology, Inc.

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

8,192 x 18

16,384 x 18

••

••

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

HF

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

LD

MRS

REN

RCLK

OE

•

•

•

•

TIMING

FS

OFFSET REGISTER

•

PRS

FWFT/SI

SEN

RT

3037 drw 01

IDT72255

IDT72265

CMOS SUPERSYNC FIFO

™

8,192 x 18, 16,384 x 18

FEATURES:

• 8,192 x 18-bit storage capacity (IDT72255)

• 16,384 x 18-bit storage capacity (IDT72265)

• 10ns read/write cycle time (8ns access time)

• Retransmit Capability

• Auto power down reduces power consumption

• Master Reset clears entire FIFO, Partial Reset clears

data, but retains programmable settings

• Empty, Full and Half-full flags signal FIFO status

• Programmable Almost Empty and Almost Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using

EF and FF flags) or

First Word Fall Through timing (using

OR and IR flags)

• Easily expandable in depth and width

• Independent read and write clocks (permit simultaneous

reading and writing with one clock signal)

• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-

pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin

Pin Grid Array (PGA)

• Output enable puts data outputs into high impedance

• High-performance submicron CMOS technology

able, tested to military electrical specifications

DESCRIPTION:

The IDT72255/72265 are monolithic, CMOS, high capac-

ity, high speed, low power First-In, First-Out (FIFO) memories

with clocked read and write controls. These FIFOs are appli-

cable for a wide variety of data buffering needs, such as optical

disk controllers, local area networks (LANs), and inter-proces-

sor communication.

clock (WCLK) and a data input enable pin (

WEN). Data is

written into the synchronous FIFO on every clock when

WEN

is asserted. The output port is controlled by another clock pin

(RCLK) and enable pin (

REN). The read clock can be tied to

the write clock for single clock operation or the two clocks can

run asynchronously for dual clock operation. An output enable

pin (

OE) is provided on the read port for three-state control of

the outputs.

The IDT72255/72265 have two modes of operation: In the

deposited into the memory array. A read operation is required

to access that word. In the

First Word Fall Through Mode

(FWFT), the first word written to an empty FIFO appears

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.