Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

IDT72265L15PF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # IDT72265L15PF
Description  CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72265L15PF Datasheet(HTML) 8 Page - Integrated Device Technology

Back Button IDT72265L15PF Datasheet HTML 4Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 5Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 6Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 7Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 8Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 9Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 10Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 11Page - Integrated Device Technology IDT72265L15PF Datasheet HTML 12Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 30 page
background image
8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18
When
OR goes LOW, Retransmit Setup is complete; at the
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on
REN to
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met:
OR is LOW or 14
cycles of the faster clock (RCLK or WCLK) have elapsed since
the RCLK rising edge enabled by the
RT pulse.
The assertion time of
OR during Retransmit Setup is
variable. The parameter tRTF2, which is measured from the
rising RCLK edge enabled by
RT to the falling edge of OR is
described by the following equation:
tRTF2 max. = 14*Tf + 4*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever
is shorter, and TRCLK is the RCLK period.
Note that a
Retransmit Setup in FWFT mode requires one more RCLK
cycle than in IDT Standard mode.
Regarding
IR: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup,
IR will
remain LOW throughout the setup procedure.
For FWFT mode, updating the
PAE, HF, and PAF flags
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts
OR and
automatically accesses the first memory location. Note that,
in this case,
REN is not required to initiate flag updating. HF
is updated on the "last" RCLK rising edge.
PAE is updated
after two more rising RCLK edges.
PAF is updated after the
"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the tskew2 specification is not met, add one more
WCLK cycle.)
RT is synchronized to RCLK. The Retransmit operation is
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state
of the FWFT/SI helps determine whether the device will
operate in IDT Standard mode or First Word Fall Through
(FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (
EF) to indicate whether or not there are any words
present in the FIFO memory. It also uses the Full Flag function
(
FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (
REN) line.
If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(
OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (
IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to Qn, no read request necessary. Subsequent words
must be accessed using the Read Enable (
REN) line.
After Master Reset, FWFT/SI acts as a serial input for
loading
PAE and PAF offsets into the programmable registers.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both IDT Standard and
FWFT modes.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the write clock
(WCLK). Data set-up and hold times must be met with respect
to the LOW-to-HIGH transition of the WCLK. The write and
read clocks can either be asynchronous or coincident.
WRITE ENABLE (
WEN
WEN)
When Write Enable (
WEN) is LOW, data can be loaded into
the input register on the rising edge of every WCLK cycle.
Data is stored in the RAM array sequentially and indepen-
dently of any on-going read operation.
When
WEN is HIGH, the input register holds the previous
data and no new data is loaded into the FIFO.
To prevent data overflow in the IDT Standard Mode,
FF will
go LOW , inhibiting further write operations. Upon the comple-
tion of a valid read cycle,
FF will go HIGH allowing a write to
occur.
WEN is ignored when the FIFO is full.
To prevent data overflow in the FWFT mode,
IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle,
IR will go LOW allowing a write to occur.
WEN is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs, on the rising edge of the
read clock (RCLK), when Output Enable (
OE) is set LOW. The
write and read clocks can be asynchronous or coincident.
READ ENABLE (
REN
REN)
When Read Enable (
REN) is LOW, data is loaded from the
RAM array into the output register on the rising edge of the
RCLK.
When
REN is HIGH, the output register holds the previous
data and no new data is loaded into the output register.
In the IDT Standard Mode, every word accessed at Qn,
including the first word written to an empty FIFO, must be
requested using
REN. When all the data has been read from
the FIFO, the Empty Flag (
EF) will go LOW, inhibiting further
read operations.
REN is ignored when the FIFO is empty.
Once a write is performed,
EF will go HIGH after tFWL1 +tREF
and a read is permitted.
In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, no need for any read
request. In order to access all other words, a read must be
executed using
REN . When all the data has been read from
the FIFO, Output Ready (
OR) will go HIGH, inhibiting further
read operations.
REN is ignored when the FIFO is empty.
Once a write is performed,
OR will go LOW after tFWL2 +tREF,
when the first word appears at Qn ; if a second word is written
into the FIFO, then
REN can be used to read it out.


Similar Part No. - IDT72265L15PF

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT72265LA IDT-IDT72265LA Datasheet
328Kb / 27P
   CMOS SuperSync FIFO
IDT72265LA IDT-IDT72265LA Datasheet
488Kb / 27P
   CMOS SuperSync FIFO
logo
Renesas Technology Corp
IDT72265LA RENESAS-IDT72265LA Datasheet
404Kb / 28P
   CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18
NOVEMBER 2017
logo
Integrated Device Techn...
IDT72265LA10PF IDT-IDT72265LA10PF Datasheet
354Kb / 27P
   CMOS SUPERSYNC FIFO
IDT72265LA10PFG IDT-IDT72265LA10PFG Datasheet
328Kb / 27P
   CMOS SuperSync FIFO
More results

Similar Description - IDT72265L15PF

ManufacturerPart #DatasheetDescription
logo
Renesas Technology Corp
IDT72255LA RENESAS-IDT72255LA Datasheet
404Kb / 28P
   CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18
NOVEMBER 2017
logo
Integrated Device Techn...
IDT72V255LA IDT-IDT72V255LA Datasheet
439Kb / 27P
   3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18
logo
Renesas Technology Corp
72V255LA RENESAS-72V255LA Datasheet
402Kb / 28P
   3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18
JANUARY 2018
logo
Integrated Device Techn...
IDT72261 IDT-IDT72261 Datasheet
388Kb / 30P
   CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72264 IDT-IDT72264 Datasheet
392Kb / 31P
   VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9
logo
Renesas Technology Corp
72V275 RENESAS-72V275 Datasheet
553Kb / 26P
   3.3 VOLT CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18
FEBRUARY 2018
IDT72261LA RENESAS-IDT72261LA Datasheet
537Kb / 28P
   CMOS SuperSync FIFO™ 16,384 x 9 32,768 x 9
FEBRUARY 2018
logo
Integrated Device Techn...
IDT72V295 IDT-IDT72V295 Datasheet
237Kb / 26P
   3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 131,072 x 18 262,144 x 18
logo
Renesas Technology Corp
72V295 RENESAS-72V295 Datasheet
391Kb / 27P
   3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™ 131,072 x 18 262,144 x 18
MARCH 2018
logo
Integrated Device Techn...
7203L25J IDT-7203L25J Datasheet
311Kb / 10P
   CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9 8,192 x 9, 16,384 x 9
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com