IDT72265L10TF datasheet(3/30 Pages) IDT

Part #	IDT72265L10TF

Description	CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72255/72265 SyncFIFO

™

8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

gramming offset registers may not be convenient.

The Retransmit function allows the read pointer to be reset

to the first location in the RAM array. It is synchronized to

RCLK when

RT is LOW. This feature is convenient for

sending the same data more than once.

If, at any time, the FIFO is not actively performing a function,

the chip will automatically power down. This occurs if neither

a read nor a write occurs within 10 cycles of the faster clock,

RCLK or WCLK. During the Power Down state, supply current

consumption (ICC2) is at a minimum. Initiating any operation

(by activating control inputs) will immediately take the device

out of the Power Down state.

The IDT72255/72265 are depth expandable. The addition

of external components is unnecessary. The

IR and OR

functions, together with

REN and WEN, are used to extend the

total FIFO memory capacity.

The FS line ensures optimal data flow through the FIFO. It

is tied to GND if the RCLK frequency is higher than the WCLK

frequency or to Vcc if the RCLK frequency is lower than the

WCLK frequency

The IDT72255/72265 is fabricated using IDT’s high speed

submicron CMOS technology.

PGA (G68-1, order code: G)

TOP VIEW

NOTES

:

1. DNC = Do not connect

D8

Pin 1 Designator

AB

C

D

E

F

G

H

J

K

L

Q0

D2

PAF

DNC

VCC

RCLK

REN

OE

GND

DNC

MRS

LD WCLK

PRS

VCC

WEN

D17

GND

D15

D16

D11

D14

D12

D10

D9

D7

D6

PAE

D4

D3

D1

D0

Q1

Q2

GND

Q3

Q4

GND

Q8

Q7

Q10

DNC

GND

VCC

Q17 Q16

Q15

Q14

Q13 Q12

Q9

HF

EF/

OR

FF/

IR

11

10

09

08

07

06

05

04

03

02

01

RT

FWFT/

SI

D13

D5

GND

VCC

GND

Q11

Q6

Q5

3037 drw 03

SEN FS

GND

PIN CONFIGURATIONS (CONT.)

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