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2001 Integrated Device Technology, Inc.

DSC-4093/1

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

3.3 VOLT DUAL CMOS SyncFIFO™

DUAL 256 X 9, DUAL 512 X 9,

DUAL 1,024 X 9, DUAL 2,048 X 9,

DUAL 4,096 X 9 , DUAL 8,192 X 9

IDT72V801

IDT72V811

IDT72V821

IDT72V831

IDT72V841

IDT72V851

APRIL 2001

The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.

.EATURES:

design flexibility and small footprint

applications

Almost-Full flags for each FIFO

STQFP)

°°°°°C to +85°°°°°C) is available

DESCRIPTION:

The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are

dual synchronous (clocked) FIFOs. The device is functionally equivalent to

two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single

package with all associated control, data, and flag lines assigned to separate

pins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data

port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,

QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,

WCLKB), and two Write Enable pins (

WENA1, WENA2, WENB1, WENB2).

DataiswrittenintoeachofthetwoarraysoneveryrisingclockedgeoftheWrite

Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are

asserted.

The output port of each FIFO bank is controlled by its associated clock pin

(RCLKA, RCLKB) and two Read Enable pins (

RENA1, RENA2, RENB1,

RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation

orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.

An Output Enable pin (

OEA, OEB) is provided on the read port of each FIFO

for three-state output control.

Each of the two FIFOs has two fixed flags, Empty (

EFA,EFB)andFull(FFA,

FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full

(

PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.

If not programmed, the programmable flags default to Empty+7 for

PAEAand

PAEB, and Full-7 for PAFA and PAFB.

The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture

lends itself to many flexible configurations such as:

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion

This FIFO is fabricated using IDT's high-performance submicron CMOS

technology.

.UNCTIONAL BLOCK DIAGRAM

WCLKA

WENA1

WENA2

LDA

OFFSET REGISTER

INPUT REGISTER

WRITE CONTROL

LOGIC

RESET LOGIC

OUTPUT REGISTER

OEA

RSA

RCLKA

RENA1

RENA2

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EFA

PAEA

PAFA

FFA

4093 drw 01

WCLKB

WENB1

WENB2

LDB

OFFSET REGISTER

INPUT REGISTER

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

OUTPUT REGISTER

OEB

RSB

RCLKB

RENB1

RENB2

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EFB

PAFB

FFB

PAEB

WRITE POINTER

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9