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IDT72V811L15PF Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT72V811L15PF
Description  3.3 VOLT DUAL CMOS SyncFIFO?
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V811L15PF Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
Figure 4. Reset Timing
NOTES:
1. Holding WENA2/
LDA (WENB2/LDB) HIGH during reset will make the pin act as a second Write Enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make
the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if
OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 5. Write Cycle Timing
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for
FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then
FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
tDH
tENH
tSKEW1(1)
tCLK
tCLKH
tCLKL
tDS
tENS
tWFF
tWFF
WCLKA (WCLKB)
(DA0 - DA8
DB0 - DB8)
WENA1
(
WENB1)
WENA2 (WENB2)
(If Applicable)
FFA
(
FFB)
RCLKA (RCLKB)
RENA1, RENA2
(
RENB1, RENB2)
NO OPERATION
NO OPERATION
4093 drw 07
DATA IN VALID
tENS
tENH
tRS
tRSR
RSA (RSB)
RENA1, RENA2
(
RENB1, RENB2)
tRSF
tRSF
OEA (OEB) = 1
OEA (OEB) = 0
(2)
EFA, PAEA
(
EFB, PAEB)
FFA, PAFA
(
FFA, PAFA)
QA0 - QA8
(QB0 - QB8)
4093 drw 06
WENA1
(
WENB1)
tRSS
tRSF
tRSR
tRSS
tRSR
tRSS
WENA2/
LDA
(WENB2/
LDB)
(1)


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