Electronic Components Datasheet Search |
|
IDT72261L20GB Datasheet(PDF) 1 Page - Integrated Device Technology |
|
IDT72261L20GB Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 30 page IDT72261 IDT72271 CMOS SUPERSYNC FIFO ™ 16,384 x 9, 32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1997 ©1997 Integrated Device Technology, Inc DSC-3036/6 1 Integrated Device Technology, Inc. SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. FUNCTIONAL BLOCK DIAGRAM FEATURES: • 16,384 x 9-bit storage capacity (IDT72261) • 32,768 x 9-bit storage capacity (IDT72271) • 10ns read/write cycle time (8ns access time) • Retransmit Capability • Auto power down reduces power consumption • Master Reset clears entire FIFO, Partial Reset clears data, but retains programmable settings • Empty, Full and Half-full flags signal FIFO status • Programmable Almost Empty and Almost Full flags, each flag can default to one of two preselected offsets • Program partial flags by either serial or parallel means • Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) • Easily expandable in depth and width • Independent read and write clocks (permit simultaneous reading and writing with one clock signal • Available in the 64-pin Thin Quad Flat Pack (TQFP), 64- pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin Pin Grid Array (PGA) • Output enable puts data outputs into high impedance • High-performance submicron CMOS technology • Industrial temperature range (-40OC to +85OC) is avail- able, tested to military electrical specifications DESCRIPTION: The IDT72261/72271 are monolithic, CMOS, high capac- ity, high speed, low power first-in, first-out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (LANs), and inter- processor communication. Both FIFOs have a 9-bit input port (Dn) and a 9-bit output port (Qn). The input port is controlled by a free-running clock (WCLK) and a data input enable pin ( WEN). Data is written into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and enable pin ( REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronously for dual clock operation. An output enable pin ( OE) is provided on the read port for three-state control of the outputs. The IDT72261/72271 have two modes of operation: In the IDT Standard Mode, the first word written to the FIFO is deposited into the memory array. A read operation is required to access that word. In the First Word Fall Through Mode (FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required. The INPUT REGISTER OUTPUT REGISTER RAM ARRAY 16,384 x 9 32,768 x 9 • • • • FLAG LOGIC FF/IR PAF EF/OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK D0-D8 LD MRS REN RCLK OE Q0-Q8 • • • • TIMING FS OFFSET REGISTER • PRS FWFT/SI SEN RT 3036 drw 01 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. |
Similar Part No. - IDT72261L20GB |
|
Similar Description - IDT72261L20GB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |