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IDT72231L25PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72231L25PF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 14 page 1 SEPTEMBER 2002 CMOSSyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72421, IDT72201 IDT72211, IDT72221 IDT72231, IDT72241 IDT72251 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2655/2 FEATURES: ••••• 64 x 9-bit organization (IDT72421) ••••• 256 x 9-bit organization (IDT72201) ••••• 512 x 9-bit organization (IDT72211) ••••• 1,024 x 9-bit organization (IDT72221) ••••• 2,048 x 9-bit organization (IDT72231) ••••• 4,096 x 9-bit organization (IDT72241) ••••• 8,192 x 9-bit organization (IDT72251) ••••• 10 ns read/write cycle time ••••• Read and Write Clocks can be independent ••••• Dual-Ported zero fall-through time architecture ••••• Empty and Full Flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags can be set to any depth ••••• Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively ••••• Output enable puts output data bus in high-impedance state ••••• Advanced submicron CMOS technology ••••• Available in the 32-pin plastic leaded chip carrier (PLCC) and 32-pin Thin Quad Flat Pack (TQFP) ••••• For through-hole product please see the IDT72420/72200/72210/ 72220/72230/72240 data sheet ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available FUNCTIONAL BLOCK DIAGRAM WCLK WEN1 WEN2 D0 - D8 LD OFFSET REGISTER INPUT REGISTER RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 WRITE CONTROL LOGIC WRITE POINTER OUTPUT REGISTER READ CONTROL LOGIC READ POINTER FLAG LOGIC EF PAE PAF FF RESET LOGIC OE REN2 REN1 RS RCLK 2655 drw01 Q0 - Q8 DESCRIPTION: The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™ are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a 64, 256, 512, 1,024, 2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are applicableforawidevarietyofdatabufferingneedssuchasgraphics,localarea networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two write enable pins ( WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two read enable pins ( REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin ( OE) is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty ( EF) and Full (FF). Two programmable flags, Almost-Empty ( PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting the load pin ( LD). These FIFOs are fabricated using IDT’s high-speed submicron CMOS technology. |
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