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IDT72255L12TFB Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72255L12TFB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 30 page 9 IDT72255/72265 SyncFIFO ™ 8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES SERIAL ENABLE ( SEN SEN) Serial Enable is ( SEN) is an enable used only for serial programming of the offset registers. The serial programming method must be selected during Master Reset. SEN is always used in conjunction with LD. When these lines are both LOW, data at the SI input can be loaded into the input register one bit for each LOW-to-HIGH transition of WCLK. When SEN is HIGH, the programmable registers retains the previous settings and no offsets are loaded. SEN functions the same way in both IDT Standard and FWFT modes. OUTPUT ENABLE ( OE OE) When Output Enable ( OE) is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high impedance state. LOAD ( LD LD) This is a dual purpose pin. During Master Reset, the state of the Load line ( LD) determines one of two default values (127 or 1023) for the PAE and PAF flags, along with the method by which these flags can be programmed, parallel or serial. After Master Reset, LD enables write operations to and read operations from the registers. Only the offset loading method currently selected can be used to write to the registers. Aside from Master Reset, there is no other way change the loading method. Registers can be read only in parallel; this can be accomplished regardless of whether serial or the parallel loading has been selected. Associated with each of the programmable flags, PAE and PAF, are registers which can either be written to or read from. Offset values contained in these registers determine how many words need to be in the FIFO memory to switch a partial flag. A LOW on LD during Master Reset selects a default PAE offset value of 07FH ( a threshold 127 words from the empty boundary), a default PAF offset value of 07FH (a threshold 127 words from the full boundary), and parallel loading of other offset values. A HIGH on LD during Master Reset selects a default PAE offset value of 3FFH (a threshold 1023 words from the empty boundary), a default PAF offset value of 3FFH (a threshold 1023 words form the full boundary), and serial loading of other offset values. The act of writing offsets (in parallel or serial) employs a dedicated write offset register pointer. The act of reading offsets employs a dedicated read offset register pointer. The Figure 2. Partial Flag Programming Sequence NOTES: 1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time. 2. The programming method can only be selected at Master Reset. 3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 4. The programming sequence applies to both IDT Standard and FWFT modes. Selection Parallel write to registers: Empty Offset Full Offset Parallel read from registers: Empty Offset Full Offset No Operation Write Memory Read Memory No Operation 3037 tbl 02 0 0 X 1 1 1 0 0 1 1 0 X 1 1 1 0 1 X 0 1 1 Serial shift into registers: 26 bits for the 72255 28 bits for the 72265 1 1 1 X X X 0 WCLK X X X X RCLK X X X X X 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) |
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