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IDT7217L16GB Datasheet(PDF) 5 Page - Integrated Device Technology

Part # IDT7217L16GB
Description  16 x 16 PARALLEL CMOS MULTIPLIERS
Download  13 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7217L16GB Datasheet(HTML) 5 Page - Integrated Device Technology

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11.3
5
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
2580 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25
°C, f = 1.0 MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
10
pF
COUT
Output Capacitance
VOUT = 0V
12
pF
NOTE:
2580 tbl 04
1. This parameter is measured at characterization and not tested.
Symbol
Rating
Commercial
Military
Unit
VCC
Power Supply
Voltage
–0.5 to +7.0
–0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect to
GND
VCC + 0.5
VCC + 0.5
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
IOUT
DC Output
Current
50
50
mA
Pin Name
I/O
Description
X0 - X15
I
Data Inputs
Y0 - Y15/
P0 - P15
I/O
Y0 - Y15 are data inputs
P0 - P15 are LSP register output, enabled when
OEL = 0
P16 - P31
O
Data Output (LSP or MSP)
OEL
I
Output enable control for LSP (least significant product). When low enables P0 - P15. When high P0 - P15
tristated.
OEP
I
Output enable control for MSP (most significant product). When low enables P16 - P31. When high P16 -
P31 tristated.
XM, YM
I
Mode control for each data word. Low designates unsigned data input and high designates two's
complement.
RND
I
"Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This
signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When
RND = 1 and FA = 0, 1 is added to the 2-16 bit (P14). The RND input is registered. It is clocked on the
rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217.
Rounding always occurs in the positive direction which may introduce a systematic bias.
MSPSEL
I
When low, MSP is output on P16 - P31 lines. When high, LSP is output on P16 - P31.
FA
I
Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product
is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's
complement applications (see multiplier input / output formats).
FT
I
Flow through control. When high, both MSP and LSP registers are by-passed.
CLK
I
7217 X, Y, RND, LSP and MSP register clock input.
CLKX
I
7216 X register clock input. Also clocks RND register.
CLKY
I
7216 Y register clock input. Also clocks RND register.
CLKL
I
7216 LSP register clock input.
CLKM
I
7216 MSP register clock input.
ENX
I
7217 X register clock enable. Also enables RND register clock.
ENY
I
7217 Y register clock enable. Also enables RND register clock.


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