7.18

2

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

LCC

TOP VIEW

DIP/SOIC/CERPACK

TOP VIEW

FUNCTION TABLE

(2)

Inputs

Data I/O

(1)

Operation or Function

G

G

DIR

CPAB

CPBA

SAB

SBA

IDT54/74FCT646

H

X

H or L

H or L

X

X

Input

Input

Isolation

HX

↑↑

X

X

Store A and B Data

L

L

X

X

X

L

Output

Input

Real-Time B Data to A Bus

L

L

X

H or L

X

H

Stored B Data to A Bus

L

H

X

X

L

X

Input

Output

Real-Time A Data to B Bus

L

H

H or L

X

H

X

Stored A Data to B Bus

NOTES:

2536 tbl 02

1. The data output functions may be enabled or disabled by various signals at the

G or DIR inputs. Data input functions are always enabled, i.e., data at

the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

2. H = HIGH, L = LOW, X = Don’t Care,

↑ = LOW-to-HIGH Transition.

PIN DESCRIPTION

Pin Names

Description

Data Register A Inputs

Data Register B Outputs

Data Register B Inputs

Data Register A Outputs

CPAB, CPBA

Clock Pulse Inputs

SAB, SBA

Output Data Source Select Inputs

DIR,

G

Output Enable Inputs

2536 tbl 01

LOGIC SYMBOL

5

6

7

8

9

10

11

12

GND

1

2

3

4

24

23

22

21

20

19

18

17

Vcc

16

15

14

13

CPAB

P24-1,

D24-1,

S024-2

&

E24-1

SAB

DIR

CPBA

SBA

G

2536 drw 06

CPAB

SAB

DIR

CPBA

SBA

G

5

6

7

8

9

10

11

L28-1

25

24

23

22

21

20

19

INDEX

2536 drw 02

G

NC

NC

12 13 14 15 16 17 18

43

2

1

28 27 26