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IDT72220L12TCB Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72220L12TCB Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 16 page 5.12 8 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO ™ 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the curent clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 3. Write Cycle Timing WCLK D0 - D7 WEN FF tCLK tCLKH tCLKL tDS tENS tDH tENH tWFF tWFF DATAIN VALID NO OPERATION RCLK (1) tSKEW1 REN 2680 drw 05 |
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