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IDT74FCT821CTD Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT74FCT821CTD Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 9 page IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.21 6 SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT821/823/825AT FCT821/823/825BT Com'l. Mil. Com'l. Mil. Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit tPLH tPHL Propagation Delay CP to YI ( OE = LOW) CL = 50pF RL = 500 Ω 1.5 10.0 1.5 11.5 1.5 7.5 1.5 8.5 ns CL = 300pF(4) RL = 500 Ω 1.5 20.0 1.5 20.0 1.5 15.0 1.5 16.0 tSU Set-up Time HIGH or LOW DI to CP CL = 50pF RL = 500 Ω 4.0 — 4.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW DI to CP 2.0 — 2.0 — 1.5 — 1.5 — ns tSU Set-up Time HIGH or LOW EN to CP 4.0 — 4.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW EN to CP 2.0 — 2.0 — 0 — 0 — ns tPHL Propagation Delay, CLR to YI 1.5 14.0 1.5 15.0 1.5 9.0 1.5 9.5 ns tREM Recovery Time CLR to CP 6.0 — 7.0 — 6.0 — 6.0 — ns tW Clock Pulse Width HIGH or LOW 7.0 — 7.0 — 6.0 — 6.0 — ns tW CLR Pulse Width LOW 6.0 — 7.0 — 6.0 — 6.0 — ns tPZH tPZL Output Enable Time OE to YI CL = 50pF RL = 500 Ω 1.5 12.0 1.5 13.0 1.5 8.0 1.5 9.0 ns CL = 300pF(4) RL = 500 Ω 1.5 23.0 1.5 25.0 1.5 15.0 1.5 16.0 tPHZ tPLZ Output Disable Time OE to Y I CL = 5pF(4) RL = 500 Ω 1.5 7.0 1.5 8.0 1.5 6.5 1.5 7.0 ns CL = 50pF RL = 500 Ω 1.5 8.0 1.5 9.0 1.5 7.5 1.5 8.0 NOTES: 2567 tbl 08 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. This condition is guaranteed but not tested. |
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