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IMP1232LPEMA Datasheet(PDF) 4 Page - IMP, Inc |
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IMP1232LPEMA Datasheet(HTML) 4 Page - IMP, Inc |
4 / 7 page 4 408-432-9100/www.impweb.com © 1999 IMP, Inc. IMP1 IMP1232LP/LPS 232LP/LPS Application Information Supply Voltage Monitor Reset Signal Polarity and Output Stage Structure RESET is an active LOW signal. It is developed with an open drain driver. If a pullup resistor is required, typical values are 10k Ω to 50kΩ. RESET is an active High signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. Trip Point Tolerance Selection With TOL connected to VCC, RESET and RESET become active whenever VCC falls below 4.5V. RESET and RESET become active when VCC falls below 4.75V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The active HIGH reset signal is valid down to a VCC level of 1.2V also. Figure 1. Timing Diagram: Power Up Figure 2. Timing Diagram: Power Down 1232_05.eps 4.75V VCCTP 4.25V VCC RESET RESET tR tRPU VOH VOL Figure 3. Timing Diagram: Pushbutton Reset VIH VIL VOH VOL RESET RESET PBRST tPDLY tPB tRST 1232_08.eps Figure 4. Application Circuit: Pushbutton Reset 1232_06.eps PBRST 5V 1 VCC TD 2 ST TOL IMP1232LP/LPS µP 3 4 RESET GND 8 7 6 5 RESET RESET 4.75V VCCTP 4.25V VCC RESET RESET tF VOH VOL tRPD 1232_04.eps Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is normally pulled HIGH through an internal 40k Ω resistor. When PBRST is held LOW for the minimum time tPB , both resets become active and remain active for approximately a minimum time period of 250ms after PBRST returns HIGH. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40k Ω resistor. The PBRST can be driven from a TTL or CMOS logic line or short- ed to ground with a mechanical switch. e c n a r e l o T t c e l e Se c n a r e l o T ) V ( e g a t l o V t n i o P P I R T n i Ml a n i m o Nx a M V = L O T C C % 0 15 2 . 47 3 . 49 4 . 4 D N G = L O T% 55 . 42 6 . 44 7 . 4 s p e . 2 0 t _ 2 3 2 1 |
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