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IA2910A

Microprogram Controller

Copyright

© 1999, InnovASIC Inc.

Customer Specific IC Solutions

forced unconditionally; or (3) tying it to the source of IA2910A instruction bit I(0), which leaves

instructions 4, 6, and 10 as data-dependent but makes others unconditional. All of these tricks save

one bit of microcode width.

The effect of three instructions depends on the contents of the register/counter. Unless the

counter holds a value of zero, it is decremented; if it does hold zero, it is held and a different

microprogram next address is selected. These instructions are useful for executing a

microinstruction loop a known number of times. Instruction 15 is affected both by the external

condition code and the internal register/counter.

Instruction 0 JZ JUMP and ZERO, or RESET unconditionally specifies that the address of the

next microinstruction is zero. Many designs use this feature for power-up sequences and provide

the power-up firmware beginning at microprogram memory word location 0.

Instruction 1 CJS is a CONDITIONAL JUMP-TO-SUBROUTINE via the address provided in

the pipeline register. As shown in Figure II, the machine might have executed words at address 50,

51, and 52. When the contents of address 52 is in the pipeline register, the next address control

function is the CJS. Here, if the test is passed, the next instruction executed will be the contents of

microprogram memory location 90. If the test has failed, the CJS will not be executed; the contents

of microprogram memory location 53 will be executed instead. Thus the CJS instruction at location

52 will cause the instruction either in location 90 or location 53 to be executed next. If the TEST

input is such that location 90 is selected, value 53 will be pushed onto the internal stack. This

provides the return linkage for the machine when the subroutine beginning at location 90 is

completed. In this example, the subroutine was completed at location 93 and a RETURN-FROM-

SUBOUTINE would be found at location 93.

Instruction 2 JMAP is the JUMP MAP instruction. This is an unconditional instruction which

causes the MAPn output to be enabled so that the next microinstruction location is determined by

the address supplied via the mapping PROMs. Normally, the JMAP instruction is used at the end

of the instruction fetch sequence for the machine. In the example of Figure II, microinstructions at

locations 50, 51, 52, and 53 might have been the fetch sequence and at its completion at location 53,

the JMAP function would be contained in the pipeline register. This example shows the mapping

PROM outputs to be 90; therefore, an unconditional jump to microprogram memory address 90 is

performed.

Instruction 3 CJP, CONDITIONAL JUMP PIPELINE, derives its branch address from the

pipeline register branch address value (BR(0) –BR(11) in FIGURE II). This instruction provides a

technique for branching to various microprogram sequences depending upon the test condition

inputs. Quite often, state machines are designed which simply execute tests on various inputs

waiting for the condition to come true. When the true condition is reached, the machine then

branches and executes a set of microinstructions to perform some function. This usually has the

effect of resetting the input being tested until some point in the future. Figure II shows the

conditional jump via the pipeline register address at location 52. When the contents of

microprogram memory word 52 are in the pipeline register, the next address will be either location

53 or location 30 in this example. If the test is passed, the value currently in the pipeline register

(30) will be contained in the microprogram counter which, in this example, is 53.