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DA28F016SA-150 Datasheet(PDF) 6 Page - Intel Corporation |
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DA28F016SA-150 Datasheet(HTML) 6 Page - Intel Corporation |
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6 / 55 page  28F016SA E 6 when writing several bytes in a row to the array or erasing several blocks at the same time. The 28F016SA can also perform program operations to one block of memory while performing erase of another block. The 28F016SA provides user-selectable block locking to protect code or data such as device drivers, PCMCIA card information, ROM-executable O/S or application code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the 28F016SA has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. The 28F016SA contains three types of Status Registers to accomplish various functions: • A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory’s Status Register. This register, when used alone, provides a straightforward upgrade capability to the 28F016SA from a 28F008SA- based design. • A Global Status Register (GSR) which informs the system of Command Queue status, Page Buffer status, and overall Write State Machine (WSM) status. • 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for byte-wide and word-wide modes are shown in Figures 5 and 6. The 28F016SA incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User’s Manual. The 28F016SA also incorporates a dual chip-enable function with two input pins, CE0# and CE1#. These pins have exactly the same functionality as the regular chip-enable pin CE# on the 28F008SA. For minimum chip designs, CE1# may be tied to ground to use CE0# as the chip enable input. The 28F016SA uses the logical combination of these two signals to enable or disable the entire chip. Both CE0# and CE1# must be active low to enable the device and, if either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices. The BYTE# pin allows either x8 or x16 read/programs to the 28F016SA. BYTE# at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 1. The 28F016SA is specified for a maximum access time of 70 ns (tACC) at 5.0V operation (4.75V to 5.25V) over the commercial temperature range (0 °C to +70°C). A corresponding maximum access time of 120 ns at 3.3V (3.0V to 3.6V and 0 °C to +70 °C) is achieved for reduced power consumption applications. The 28F016SA incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in the static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5.0V (0.8 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 1.0 µA, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time is required from RP# switching high until outputs are again valid. In the deep power-down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 50 µA. 2.0 DEVICE PINOUT The 28F016SA 56-lead TSOP Type I pinout configuration is shown in Figure 2. The 56-lead SSOP pinout configuration is shown in Figure 3. |
Similar Part No. - DA28F016SA-150 |
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Similar Description - DA28F016SA-150 |
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