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TE28F020-150 Datasheet(PDF) 6 Page - Intel Corporation |
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TE28F020-150 Datasheet(HTML) 6 Page - Intel Corporation |
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6 / 38 page  28F020 E 6 Erase Voltage Switch Input/Output Buffers PGM Voltage Switch Chip Enable Output Enable Logic Data Latch State Control Command Register Integrated Stop Timer Y-Decoder X-Decoder Y-Gating 2,097,152 Bit Cell Matrix To Array Source V CC V SS V PP WE# CE# OE# A 0 - A17 STB STB DQ 0 - DQ7 0245_01 Figure 1. 28F020 Block Diagram Table 1. Pin Description Symbol Type Name and Function A0–A17 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. DQ0–DQ7 INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data during memory read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE# is active low; CE# high deselects the memory device and reduces power consumption to standby levels. OE# INPUT OUTPUT ENABLE: Gates the devices output through the data buffers during a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the control register and the array. Write enable is active low. Addresses are latched on the falling edge and data is latched on the rising edge of the WE# pulse. Note: With VPP ≤ 6.5 V, memory contents cannot be altered. VPP ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing the entire array, or programming bytes in the array. VCC DEVICE POWER SUPPLY (5 V ±10%) VSS GROUND |
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