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74ALVCH245PG Datasheet(PDF) 1 Page - Integrated Device Technology |
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74ALVCH245PG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 7 page MILITARYANDINDUSTRIALTEMPERATURERANGES IDT54/74FCT273T/AT/CT FASTCMOSOCTALDFLIP-FLOPWITHMASTERRESET 1 JUNE 2002 MILITARY AND INDUSTRIAL TEMPERATURE RANGES The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2002 Integrated Device Technology, Inc. DSC-2568/2 FEATURES: • Std., A, and C grades • Low input and output leakage ≤≤≤≤≤1µA (max.) • CMOS power levels • True TTL input and output compatibility: –VOH = 3.3V (typ.) –VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) • Power off disable outputs permit "live insertion" • Available in the following packages: – Industrial: SOIC, SSOP, QSOP – Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET DESCRIPTION: The FCT273T is an octal D flip-flop built using an advanced dual metal CMOS technology. The FCT273T has eight edge-triggered D-type flip- flops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set- up time before the low-to-high clock transition, is transferred to the corre- sponding flip-flop’s O output. All outputs will be forced low independently of Clock or Data inputs by a low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. D CP Q RD D0 O 0 D CP Q RD D1 O 1 D CP Q RD D2 O 2 D CP Q RD D3 O 3 D CP Q RD D4 O 4 D CP Q RD D5 O 5 D CP Q RD D6 O 6 D CP Q RD D7 O 7 CP MR |
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