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AD5255 Datasheet(PDF) 4 Page - Analog Devices |
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AD5255 Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page AD5255 Rev. A | Page 4 of 20 Parameter Symbol Conditions Min Typ1 Max Unit DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V, VSS = 0 V 2.4 V VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V Input Logic Low VIL VDD = 5 V, VSS = 0 V 0.8 V VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V Output Logic High (SDA) VOH RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V Output Logic Low VOL RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V WP Leakage Current I WP WP = VDD 9 μA A0 Leakage Current IA0 A0 = GND 3 μA Input Leakage Current (Excluding WPand A0) II VIN = 0 V or VDD ±1 μA Input Capacitance5 CI 5 pF POWER SUPPLIES Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V Dual-Supply Power Range VDD/VSS ±2.2 5 ±2.7 5 V Positive Supply Current IDD VIH = VDD or VIL = GND, VSS = 0 V 5 15 μA Negative Supply Current ISS VIH = VDD or VIL = GND, VDD = 2.5 V, VSS = −2.5 V −5 −15 μA EEMEM Data Storing Mode Current IDD_STORE VIH = VDD or VIL = GND 35 mA EEMEM Data Restoring Mode Current IDD_RESTORE VIH = VDD or VIL = GND 2.5 mA Power Dissipation7 PDISS VIH = VDD = 5 V or VIL = GND 25 75 μW Power Supply Sensitivity5 PSS ∆VDD = 5 V ± 10% 0.01 0.025 %/% 1 Typical represents average readings at 25°C, VDD = 5 V. 2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. 4 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. t1 t2 t3 t8 t8 t9 t9 t6 t4 t7 t5 t2 t10 PS S SCL SDA P Figure 2. I2C Timing Diagram |
Similar Part No. - AD5255_15 |
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Similar Description - AD5255_15 |
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