AD5383_15 datasheet(1/40 Pages) AD

Part #	AD5383

Description	32-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC

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32-Channel, 3 V/5 V, Single-Supply,

12-Bit, denseDAC

Data Sheet

AD5383

FEATURES

Guaranteed monotonic

INL error: ±1 LSB max

On-chip 1.25 V/2.5 V, 10 ppm/°C reference

Temperature range: –40°C to +85°C

Rail-to-rail output amplifier

Power-down mode

Package type: 100-lead LQFP (14 mm × 14 mm)

User Interfaces

Parallel

Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,

featuring data readback)

I2C-compatible

Robust 6.5 kV HBM and 2 kV FICDM ESD rating

INTEGRATED FUNCTIONS

Channel monitor

Simultaneous output update via LDAC

Clear function to user-programmable code

Amplifier boost mode to optimize slew rate

User programmable offset and gain adjust

Toggle mode enables square wave generation

Thermal monitor

APPLICATIONS

Variable optical attenuators (VOA)

Level setting (ATE)

Optical microelectro-mechanical systems (MEMS)

Control systems

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

R

VOUT0

DAC 0

DAC

REG 0

INPUT

REG 0

12

m REG 0

c REG 0

1.25V/2.5V

REFERENCE

POWER-ON

RESET

R

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

DAC 1

DAC

REG 1

INPUT

REG 1

12

m REG 1

c REG 1

R

VOUT6

DAC 6

DAC

REG 6

INPUT

REG 6

12

m REG 6

c REG 6

R

VOUT7

VOUT8

DAC 7

DAC

REG 7

INPUT

REG 7

12

m REG 7

c REG 7

×4

FIFO

+

STATE

MACHINE

+

CONTROL

LOGIC

INTERFACE

CONTROL

LOGIC

DB11/(DIN/SDA)

DB10/(SCLK/SCL)

DB9/(SPI/I2C)

DB8

A4

A0

REG 0

REG 1

RESET

BUSY

CLR

MON_IN1

MON_IN2

MON_IN3

MON_IN4

PD

SER/PAR

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO

36-TO-1

MUX

VOUT0………VOUT31

MON_OUT

LDAC

VOUT31

DVDD (×3)

DGND (

×3)

AVDD (×4)

AGND (

×4)

DAC GND (

×4)

REFGND

REFOUT/REFIN

SIGNAL GND (

×4)

AD5383

DB0

Figure 1.

Rev. D

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Tel: 781.329.4700

Technical Support

www.analog.com

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