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IDT7132LA25FB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7132LA25FB Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 16 page 1 ©2004 Integrated Device Technology, Inc. JUNE 2004 DSC-2692/16 HIGH SPEED 2K x 8 DUAL PORT STATIC RAM IDT7132SA/LA IDT7142SA/LA Functional Block Diagram Features ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial:20/25/35/55/100ns(max.) – Industrial: 25ns (max.) – Military:25/35/55/100ns(max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT7132/42SA Active: 325mW (typ.) Standby: 5mW (typ.) – IDT7132/42LA Active: 325mW (typ.) Standby: 1mW (typ.) NOTES: 1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270 Ω. IDT7142 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270 Ω. ◆ ◆ ◆ ◆ ◆ MASTERIDT7132easilyexpandsdatabuswidthto16-or-more bits using SLAVE IDT7142 ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic (IDT7132 only) ◆ ◆ ◆ ◆ ◆ BUSY output flag on IDT7132; BUSY input on IDT7142 ◆ ◆ ◆ ◆ ◆ Battery backup operation —2V data retention (LA only) ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 5V ±10% power supply ◆ ◆ ◆ ◆ ◆ Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC packages ◆ ◆ ◆ ◆ ◆ Military product compliant to MIL-PRF-38535 QML ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds OEL CEL R/WL I/OOL-I/O7L BUSYL(1,2) A10L A0L CEL OEL R/ WL CER OER R/ WR OER CER R/ WR I/OOR-I/O7R BUSYR(1,2) A10R A0R I/O Control I/O Control Address Decoder Address Decoder MEMORY ARRAY ARBITRATION LOGIC 2692 drw 01 m 11 11 |
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