UPI-41AH42AH

SYNC MODE

The Sync Mode is provided to ease the design of

multiple controller circuits by allowing the designer

to force the device into known phase and state time

The Sync Mode may also be utilized by automatic

test equipment (ATE) for quick easy and efficient

synchronizing between the tester and the DUT (de-

vice under test)

Sync Mode is enabled when SS pin is raised to high

voltage level of a12 volts To begin synchroniza-

tion T0 is raised to 5 volts at least four clock cycles

after SS T0 must be high for at least four X1 clock

cycles to fully reset the prescaler and time state

generators T0 may then be brought down during

low state of X1 Two clock cycles later with the ris-

ing edge of X1 the device enters into Time State 1

Phase 1 SS is then brought down to 5 volts 4 clocks

later after T0 RESET is allowed to go high 5 tCY (75

clocks) later for normal execution of code

SYNC MODE TIMING DIAGRAMS

210393 – 28

Minimum Specifications

NOTE

The rising and falling edges of T0 should occur during low state of XTAL1 clock

10