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CD82C86H-5 Datasheet(PDF) 3 Page - Intersil Corporation |
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CD82C86H-5 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 8 page 4-319 82C86H Functional Diagram Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switch- ing threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indetermi- nate logic state at the inputs and cause a disruption in device operation. The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower N-channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input cir- cuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condi- tion will occur only during the time the device is in the trans- parent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10 µA during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices. Decoupling Capacitors The transient current required to charge and discharge the 300pF load capacitance specified in the 82C86H/87H data sheet is determined by: Assuming that all outputs change state at the same time and that dv/dt is constant; where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out- puts. This current spike may cause a large negative voltage spike on VCC which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1 µF ceramic disc capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible. T B7 B6 B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 A6 A7 OE IC L dv dt ⁄ () = (EQ. 1) IC L VCC 80% × () tR tF ⁄ ------------------------------------- = (EQ. 2) I 80 300 10 12 – × × () 5.0V 0.8 × () 20 10 9 – × () ⁄ × = 480mA = (EQ. 3) STB DATA IN VCC P N VCC INTERNAL DATA P P N N FIGURE 1. 82C82/83H DATA IN INTERNAL DATA VCC VCC N N P P P N OE FIGURE 2. 82C86H/87H GATED INPUTS 82C86H |
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