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SN65HVD96 Datasheet(PDF) 4 Page - Texas Instruments |
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SN65HVD96 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 15 page SN65HVD96 SLLSE35 A – JUNE 2010 – REVISED DECEMBER 2010 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER trise , tfall Driver differential output rise/fall time 15 30 ns tpAP , tpPA Driver propagation delay 40 80 ns RL= 54 Ω, CL= 50 pF, See Figure 3 Driver differential output pulse skew, tSK(P) 1 10 ns |tpAP – tpPA| D = GND, RL= 54 Ω, CL= 50 pF, tpZA, tpAZ Driver enable/disable time 50 80 ns See Figure 4 RECEIVER trise, tfall Receiver output rise/fall time 8 15 ns tPHL , tPLH Receiver propagation delay time CL= 15 pF, See Figure 5 70 90 ns tSK(P) Receiver output pulse skew,|tPHL – tPLH| 5 15 ns tPZL, tPZH, Receiver enable/disable time See Figure 6 20 100 ns tPLZ, tPHZ FUNCTION TABLE DRIVER DE D VOD L or OPEN X Z Driver Disabled (Passive) L H Driver Active H H or Open Z Driver Passive RECEIVER RE VID R H or OPEN X Z Receiver Disabled VID < –0.9 V L Active Bit Received –0.9 V < VID < –0.5 ? Indeterminate bus –0.5 V < VID < 0.5 V H Passive Bit Received L 0.5 V < VID < 0.9 V ? Indeterminate bus 0.9 V < VID L Active Bit Received Open, Short, Idle H Failsafe Condition 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD96 |
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