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P8254 Datasheet(PDF) 4 Page - Intersil Corporation |
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P8254 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 17 page 4-4 Control Word Register The Control Word Register (Figure 2) is selected by the Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 82C54, the data is stored in the Con- trol Word Register and is interpreted as a Control Word used to define the Counter operation. The Control Word Register can only be written to; status information is available with the Read-Back Command. Counter 0, Counter 1, Counter 2 These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a signal counter is shown in Figure 3. The counters are fully independent. Each Counter may operate in a different Mode. The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates. The status register, shown in the figure, when latched, con- tains the current contents of the Control Word Register and status of the output and null count flag. (See detailed expla- nation of the Read-Back command.) The actual counter is labeled CE (for Counting Element). It is a 16-bit presettable synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for “Output Latch”; the subscripts M and L for “Most significant byte” and “Least significant byte”, respectively. Both are normally referred to as one unit and called just OL. These latches normally “fol- low” the CE, but if a suitable Counter Latch Command is sent to the 82C54, the latches “latch” the present count until read by the CPU and then return to “following” the CE. One latch at a time is enabled by the counter’s Control Logic to drive the inter- nal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; when- ever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for “Count Register”). Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simulta- neously. CRM and CRL are cleared when the Counter is pro- grammed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. Note that the CE cannot be written into; whenever a count is written, it is written into the CR. The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic. 82C54 System Interface The 82C54 is treated by the system software as an array of peripheral I/O ports; three are counters and the fourth is a control register for MODE programming. Basically, the select inputs A0, A1 connect to the A0, A1 address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder. READ/ WRITE LOGIC DATA/ BUS BUFFER OUT 2 GATE 2 CLK 2 OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 CLK 0 WR RD D7 - D0 A0 A1 CS FIGURE 2. CONTROL WORD REGISTER AND COUNTER FUNCTIONS 8 CONTROL WORD REGISTER COUNTER 2 COUNTER 1 COUNTER 0 INTERNAL BUS CONTROL LOGIC CONTROL WORD REGISTER STATUS LATCH STATUS REGISTER CLK n GATE n OUT n OLM OLL CE CRM CRL FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM 82C54 |
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