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W78IRD2 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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W78IRD2 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
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6 / 76 page  W78IRD2 - 6 - 5. FUNCTIONAL DESCRIPTION The W78IRD2 architecture consists of a core processor that supports 111 different op-codes and references 64 KB of program space and 64 KB of data space. It is surrounded by various registers; four general-purpose I/O ports; one special-purpose, programmable, 4-bit I/O port; 256 bytes of RAM; 1 KB of auxiliary RAM (AUX-RAM); three timer/counters; a serial port; and an internal 74373 latch and 74244 buffer which can be switched to port 2. This section introduces the RAM, Timers/Counters, Clock, Power Management, Reduce EMI Emission, and Reset. 5.1 RAM The W78IRD2 has two banks of RAM: 256 bytes of RAM and 1 KB of AUX-RAM. AUX-RAM is enabled by clearing bit 1 in the AUXR register, and it is enabled after reset. Different addresses in RAM are addressed in different ways. • RAM 00H − 7FH can be addressed directly or indirectly, as in the 8051. The address pointers are R0 and R1 of the selected bank. • RAM 80H − FFH can only be addressed indirectly, as in the 8051. The address pointers are R0 and R1 of the selected bank. • AUX-RAM 00H −3FFH is addressed indirectly in the same way external data memory is accessed with the MOVX instruction. The address pointers are R0 and R1 of the selected bank and the DPTR register. • Addresses higher than 3FFH are stored in external memory and are accessed indirectly with the MOVX instruction, as in the 8051. When AUX-RAM is enabled, the instruction "MOVX @Ri" always accesses AUX-RAM. When the W78IRD2 is executing instructions from internal program memory, accessing AUX-RAM does not affect ports P0, P2, WR or RD . For example, ANL AUXR,#11111101B ; Enable AUX-RAM MOV DPTR,#1234H MOV A,#56H MOVX @DPTR,A ; Write 56h to address 1234H in external memory MOV XRAMAH,#02H ; Only 2 LSB effective MOV R0,#34H MOV A,@R0 ; Read AUX-RAM data at address 0234H 5.2 Timers/Counters The W78IRD2 has three timers/counters called Timer 0, Timer 1, and Timer 2. Each timer/counter consists of two 8-bit data registers: TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The operations of Timer 0 and Timer 1 are similar to those in the W78C52, and these timers are controlled by the TCON and TMOD registers. Timer 2 is controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has |
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