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ACTS00MS Datasheet(PDF) 1 Page - Intersil Corporation

Part # ACTS00MS
Description  Radiation Hardened Quad 2-Input NAND Gate
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ACTS00MS Datasheet(HTML) 1 Page - Intersil Corporation

  ACTS00MS Datasheet HTML 1Page - Intersil Corporation ACTS00MS Datasheet HTML 2Page - Intersil Corporation ACTS00MS Datasheet HTML 3Page - Intersil Corporation ACTS00MS Datasheet HTML 4Page - Intersil Corporation ACTS00MS Datasheet HTML 5Page - Intersil Corporation ACTS00MS Datasheet HTML 6Page - Intersil Corporation ACTS00MS Datasheet HTML 7Page - Intersil Corporation ACTS00MS Datasheet HTML 8Page - Intersil Corporation  
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright
© Intersil Corporation 1999
ACTS00MS
Radiation Hardened
Quad 2-Input NAND Gate
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2V Min
• Input Current
≤1µA at VOL, VOH
Description
The Intersil ACTS00MS is a radiation hardened quad 2-Input NAND
gate. A high logic level on both inputs forces the output to a logic low
state.
The ACTS00MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
April 1995
Spec Number
518822
File Number
3564.1
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C
TOP VIEW
14 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
VCC
B4
A4
Y4
B3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
A1
B1
Y1
A2
B2
Y2
GND
VCC
B4
A4
Y4
B3
A3
Y3
Truth Table
INPUTS
OUTPUT
An
Bn
Yn
LL
H
LH
H
HLH
HH
L
NOTE: L = Logic Level Low, H = Logic Level High
Functional Diagram
An
Bn
Yn
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
ACTS00DMSR
-55oC to +125oC
Intersil Class S Equivalent
14 Lead SBDIP
ACTS00KMSR
-55oC to +125oC
Intersil Class S Equivalent
14 Lead Ceramic Flatpack
ACTS00D/Sample
+25oC
Sample
14 Lead SBDIP
ACTS00K/Sample
+25oC
Sample
14 Lead Ceramic Flatpack
ACTS00HMSR
+25oC
Die
Die


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