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AD7545AN Datasheet(PDF) 4 Page - Intersil Corporation |
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AD7545AN Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 7 page 10-13 Circuit Information - D/A Converter Section Figure 2 shows a simplified circuit of the D/A converter section of the AD7545. Note that the ladder termination resistor is connected to AGND. R is typically 11k Ω. The binary weighted currents are switched between the OUT1 bus line and AGND by N-Channel switches, thus maintaining a constant current in each ladder leg independent of the switch state. One of the current switches is shown in Figure 3. The capacitance at the OUT1 bus line, COUT1, is code dependent and varies from 70pF (all switches to AGND) to 200pF (all switches to OUT1). The input resistance at VREF (Figure 2) is always equal to RLDR (RLDR is the R/2R ladder characteristic resistance and is equal to the value “R”). Since RIN at the VREF pin is constant, the reference terminal can be driven by a reference voltage or a reference current, AC or DC, of positive or negative polarity. (If a current source is used, a low temperature coefficient external RFB is recommended to define scale factor). Circuit Information - Digital Section Figure 4 shows the digital structure for one bit. The digital signals CONTROL and CONTROL are generated from CS and WR. The input buffers are simple CMOS inverters designed such that when the AD7545 is operated with VDD = 5V, the buffers convert TTL input levels (2.4V and 0.8V) into CMOS logic levels. When VIN is in the region of 2.0V to 3.5V the input buffers operate in their linear region and draw current from the power supply. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (VDD and DGND) as is practically possible. The AD7545 may be operated with any supply voltage in the range 5V ≤ VDD ≤ 15V. With VDD = +15V the input logic levels are CMOS compatible only, i.e., 1.5V and 13.5V. Application Output Offset CMOS current-steering D/A converters exhibit a code dependent output resistance which in turn causes a code dependent amplifier noise gain. The effect is a code depen- dent differential nonlinearity term at the amplifier output which depends on VOS where VOS is the amplifier input offset voltage. To maintain monotonic operation it is recom- mended that VOS be no greater than (25 x 10 -6) (V REF) over the temperature range of operation. General Ground Management AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7545. In more complex systems where the AGND and DGND con- nection is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7545 AGND and DGND pins (1N914 or equivalent). Digital Glitches When WR and CS are both low the latched are transparent and the D/A converter inputs follow the data inputs. In some MODE SELECTION WRITE MODE: CS and WR low, DAC responds to data bus (DB0 - DB11) inputs HOLD MODE: Either CS or WR high, data bus (DB0 - DB11) is locked out; DAC holds last data present when WR or CS assumed high state. NOTES: 9. VDD = +5V; tr = tf = 20ns 10. VDD = +15V; tr = tf = 40ns 11. All input signal rise and fall times measured from 10% to 90% of VDD. 12. Timing measurement reference level is (VIH + VIL)/2. 13. Since input data latches are transparent for CS and WR both low, it is preferred to have data valid before CS and WR both go low. This prevents undesirable changes at the analog output while the data inputs settle. DB11 (MSB) VREF RR R R 2R 2R 2R 2R 2R 2R RFB OUT1 AGND DB10 DB9 DB1 DB0 (LSB) FIGURE 2. SIMPLIFIED D/A CIRCUIT OF AD7545 TO LADDER FROM INTERFACE LOGIC AGND OUT1 FIGURE 3. N-CHANNEL CURRENT STEERING SWITCH FIGURE 4. DIGITAL INPUT STRUCTURE CONTROL CONTROL INPUTS BUFFERS TO OUT1 SWITCH TO AGND SWITCH AD7545 |
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