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AD7641 Datasheet(PDF) 6 Page - Analog Devices |
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AD7641 Datasheet(HTML) 6 Page - Analog Devices |
6 / 28 page AD7641 Rev. 0 | Page 6 of 28 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns Internal SCLK Period Minimum t19 8 16 32 64 ns Internal SCLK Period Maximum t19 14 26 52 103 ns Internal SCLK High Minimum t20 2 6 15 31 ns Internal SCLK Low Minimum t21 3 7 16 32 ns SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns BUSY High Width Maximum t24 0.630 0.870 1.350 2.28 μs NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. 500µAIOL 500µAIOH 1.4V TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF 0.8V 2V 2V 0.8V 0.8V 2V tDELAY tDELAY Figure 3. Voltage Reference Levels for Timing |
Similar Part No. - AD7641_15 |
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Similar Description - AD7641_15 |
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