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CA3318CM Datasheet(PDF) 9 Page - Intersil Corporation |
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CA3318CM Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 12 page 4-17 1/ 4 Point Trims The 1/4, 1/ 2 and 3/ 4 points on the reference ladder are brought out for linearity adjusting or if the user wishes to create a nonlinear transfer function. The 1/4 points can be driven by the reference drivers shown (Figure 12) or by 2-K pots connected between VREF+ and VREF-. The 1/ 2 (mid-) point should be set first by applying an input of 257/512 x (VREF) and adjusting for an output changing from 128 to 129. Similarly the 1/4 and 3/ 4 points can be set with inputs of 129/512 and 385/512 x (VREF) and adjusting for counts of 192 to 193 and 64 to 65. (Note that the points are actually 1/ 4, 1/ 2 and 3/ 4 of full scale +1 LSB.) 9-Bit Resolution To obtain 9-bit resolution, two CA3318s can be wired together. Necessary ingredients include an open-ended ladder net- work, an overflow indicator, three-state outputs, and chip- enable controls - all of which are available on the CA3318. The first step for connecting a 9-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 13. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. The overflow output of the lower device now becomes the ninth bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overtlow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The three- state outputs of the two devices (bits 1 through 8) are now connected in parallel to complete the circuitry. The complete circuit for a 9-bit A/D converter is shown in Figure 13. Grounding/Bypassing The analog and digital supply grounds of a system should be kept separate and only connected at the A/D. This keeps digital ground noise out of the analog data to be converted. Reference drivers, input amps, reference taps, and the VAA supply should be bypassed at the A/D to the analog side of the ground. See Figure 15 for a block diagram of this con- cept. All capacitors shown should be low impedance 0.1 µF ceramics and should be mounted as close to the A/D as pos- sible. If VAA+ is derived from VDD, a small (10Ω resistor or inductor and additional filtering (4.7 µF tantalum) may be used to keep digital noise out of the analog system. Input Loading The CA3318 outputs a current pulse to the VlN terminal at the start of every sample period. This is due to capacitor charging and switch feedthrough and varies with input volt- age and sampling rate. The signal source must be capable of recovering from the pulse before the end of the sample period to guarantee a valid signal for the A/D to convert. Suitable high speed amplifiers include the HA-5033, HA-2542; and CA3450. Figure 16 is an example of an ampli- fier which recovers fast enough for sampling at 15MHz. Output Loading The CMOS digital output stage, although capable of driving large loads, will reflect these loads into the local ground. It is recommended that a local QMOS buffer such as CD74HC541 E be used to isolate capacitive loads. Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from fullscale for all these tests. Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. +10V TO 30V INPUT 3 2 1 8 4 7 6 + 10 µF, TAN 18 Ω (NOTE) 5K IOT VREF+ (PIN 22) 4.7 µF, CW (NOTE) 1.5K CA3085E + TAN/IOV NOTE: Bypass VREF+ to analog GND near A/D with 0.1µF ceramic cap. Parts noted should have low temperature drift. FIGURE 11. TYPICAL VOLTAGE REFERENCE SOURCE FOR DRIVING VREF+ INPUT 10 Ω 3/ 4 REF (PIN 23) 10 Ω 1/ 2 REF (PIN 20) 10 Ω 1/ 4 REF (PIN 10) CW CW CW VREF+ (PIN 22) 1K IOT 510 Ω +10V TO +30V 3 4 11 2 1 1K IOT 1K IOT 510 Ω 7 8 5 6 10 9 + - + - + - NOTES: 1. All Op Amps = 3/4 CA324E. 2. Bypass all reference points to analog ground near A/D with 0.1 µF ceramic caps. 3. Adjust VREF+ first, then 1/ 3, 3/ 4 and 1/ 4 points. FIGURE 12. TYPICAL 1/4 POINT DRIVERS FOR ADJUSTING LINEARITY (USE FOR MAXIMUM LINEARITY) CA3318 |
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