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CA3310M Datasheet(HTML) 13 Page - Intersil Corporation

Part No. CA3310M
Description  CMOS, 10-Bit, A/D Converters with Internal Track and Hold
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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CA3310M Datasheet(HTML) 13 Page - Intersil Corporation

 
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6-18
Other Accuracy Effects
Linearity, offset, and gain errors are dependent on the
magnitude of the full-scale input range, VREF+ - VREF-.
Figure 11 shows how these errors vary with full-scale range.
The clocking speed is a second factor that affects conversion
accuracy. Figure 12 shows the typical variation of linearity,
offset, and gain errors versus clocking speed.
Gain and offset drift due to temperature are kept very low by
means of auto-balancing the comparator. The specifications
show typical offset and gain dependency on temperature.
There is also very little linearity change with temperature, only
that caused by the slight slowing of CMOS with increasing
temperature. At 85oC, for instance, the lLE and DLE would be
typically those for a 20% faster clock than at 25oC.
Power Supplies and Grounding
VDD(+) and VSS(GND) are the digital supply pins: they
operate all internal logic and the output drivers. Because the
output drivers can cause fast current spikes in the VDD and
VSS lines, VSS should have a low impedance path to digital
ground and VDD should be well bypassed.
Except for VDD+, which is a substrate connection to VDD, all
pins have protection diodes connected to VDD and VSS:
input transients above VDD or below VSS will get steered to
the digital supplies. Current on these pins must be limited by
external means to the values specified under maximum
ratings.
The VAA+ and VAA- terminals supply the charge-balancing
comparator only. Because the comparator is autobalanced
between conversions, it has good low frequency supply
rejection. It does not reject well at high frequencies, how-
ever: VAA- should be returned to a clean analog ground, and
VAA+ should be RC decoupled from the digital supply.
There is approximately 50
Ω of substrate impedance
between VDD and VAA+. This can be used, for example, as
part of a low-pass RC filter to attenuate switching supply
noise. A 10pF capacitor from VAA+ to ground would
attenuate 30kHz noise by approximately 40dB. Note that
back-to-back diodes should be placed from VDD to VAA+ to
handle supply to capacitor turn-on or turn-off current
spikes.
Figure 16 shows VAA+ supply rejection versus frequency.
Note that the frequency to be rejected scales with the clock:
the 100Hz rejection with a 100kHz clock would be roughly
equivalent to the 1kHz rejection with a 1MHz clock.
The supply current for the CA3310 is dependent on clock
frequency, supply voltage, and temperature. Figure 14
shows the typical current versus frequency and voltage,
while Figure 15 shows it versus temperature and voltage.
Note that if stopped in auto-balance, the supply current is
typically
somewhat
higher
than
if
free-running.
See
Specifications.
Application Circuits
Differential Input A/D System
As the CA3310 accepts a unipolar positive-analog input, the
accommodation of other ranges requires additional circuitry.
The input capacitance and the input energy also force using
a low-impedance source for all but slow speed use. Figure
20 shows the CA3310 with a reference, input amplifier, and
input-scaling resistors for several input ranges.
The ICL7663S regulator was chosen as the reference, as it
can deliver less than 0.25V input-to-output (dropout) voltage
and uses very little power. As high a reference as possible is
generally desirable, resulting in the best linearity and
rejection of noise at the CA3310.
The tantalum capacitor sources the VREF current spikes
during a conversion cycle. This relieves the response and
peak current requirements of the reference.
The CA3140 operational amplifier provides good slewing
capability for high bandwidth input signals and can quickly
settle the energy that the CA3310 outputs at its VlN terminal.
It can also drive close to the negative supply rail.
If system supply sequencing or an unknown input voltage is
likely to cause the operational amplifier to drive above the
VDD supply, a diode clamp can be added from pin 8 of the
operational amplifier to the VDD supply. The minus drive
current is low enough not to require protection.
With a 2MHz clock (~150kHz sampling), Nyquist criteria would
give a maximum input bandwidth of 75kHz. The resistor values
chosen are low enough to not seriously degrade system band-
width (an operational amplifier settling) at that clock frequency.
If A/D clock frequency and bandwidth requirements are lower,
the resistor values (and input impedance) can be made
correspondingly higher.
The A/D system would generally be calibrated by tying VlN- to
ground and applying a voltage to VIN+ that is 0.5 LSB (
1/
2048
of full-scale range) above ground. The operational amplifier
offset should be adjusted for an output code dithering between
00016 and 00116 for unipolar use, or 10016 and 10116 for bipo-
lar use. The gain would then be adjusted by applying a voltage
that is 1.5 LSB below the positive full scale input, and adjusting
the reference for an output dithering between 3FE16 and
3FF16.
Note that R1 through R5 should be very well matched, as
they affect the common-mode rejection of the A/D system.
Also, if R2 and R3 are not matched, the offset adjust of the
operational amplifier may not have enough adjustment range
in bipolar systems.
The common-mode input range of the system is set by the
supply voltage available to the operational amplifier. The
range that can be applied to the VIN- terminal can be
calculated by:
VIN- for the most negative,
(VIN+ -2.5V) - (
)VREF+ for the most positive.
R4
R5
--------
1
+


R4
R5
--------
1
+


R4
R5
--------
CA3310, CA3310A


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