7-658

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4006BMS

CMOS 18-Stage Static Register

Pinout

CD4006BM

TOP VIEW

Functional Diagram

D1

D1 + 4’

CLOCK

D2

D3

D4

VSS

VDD

D1 + 4

D2 + 5

D2 + 4

D3 + 4

D4 + 5

D4 + 4

1

2

3

4

5

6

7

14

13

12

11

10

9

8

LATCH

4

STAGE

4

STAGE

4

STAGE

1

STAGE

1

STAGE

4

STAGE

VSS

7

8

9

10

11

12

2

13

1

4

3

5

6

14

VDD

D1 + 4

D1 + 4’

D2 + 5

D2 + 4

D3 + 4

D4 + 5

D4 + 4

D4

D3

CLOCK

D2

D1

Features

• High-Voltage Type (20V Rating)

• Fully Static Operation

• Shifting Rates Up to 12MHz at 10V (typ)

• Permanent Register Storage with Clock Line High or

Low - No Information Recirculation Required

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Stan-

dards No. 13B, “Standard Specifications for Descrip-

tion of “B” Series CMOS Devices”

Applications

• Serial Shift Registers

• Frequency Division

• Time Delay Circuits

Description

CD4006BMS types are composed of 4 separate shift register

sections: two sections of four stages and two sections of five

stages with an output tap at the fourth stage. Each section has

an independent single-rail data path.

A common clock signal is used for all stages. Data are shifted

to the next stages on negative-going transitions of the clock.

Through appropriate connections of inputs and outputs, multi-

ple register sections of 4, 5, 8, and 9 stages or single register

sections of 10, 12, 13, 14, 16, 17 and 18 stages can be imple-

mented using one CD4006BMS package. Longer shift register

sections can be assembled by using more than one

CD4006BMS.

To facilitate cascading stages when clock rise and fall times are

slow, an optional output (D1 + 4’) that is delayed one-half clock-

cycle, is provided (see Truth Table for Output from Term. 2).

The CD4006BMS is supplied in these 14 lead outline pack-

ages:

Braze Seal DIP

H4Q

Frit Seal DIP

H6D

Ceramic Flatpack H4F

December 1992

File Number

3290