AD7841

–9–

Power-On with

CLR Low

The output stage of the AD7841 has been designed to allow

output stability during power-on. If

CLR is kept low during

power-on, then just after power is applied to the AD7841, the

DUTGND

R

R

14k

DAC

Low

Ω resistor. This thin-film resistor is connected in

parallel with the gain resistors of the output amplifier. The

amplifier’s output is thus at the same voltage as the DUTGND

pin. The output stage remains configured as in Figure 5 until

–3 V. By now the output amplifier has enough headroom to

handle signals at its input and has also had time to settle. The

The DUTGND voltage is still connected to the noninverting

DUTGND

R

R

14k

DAC

Low

via the configuration shown in Figure 6.

When

CLR is taken back high, the output stage is configured as

pins is determined by the data present in the DAC registers.

DUTGND

R

R

14k

DAC

Figure 7. Output Stage After

CLR Is Taken High

Power-On with

CLR High

If

CLR is high on the application of power to the device, the

output stages of the AD7841 are configured as in Figure 8 while

through a 14 k

Ω resistor until V

negative than –3 V.

DUTGND

R

R

14k

DAC

Figure 8. Output Stage Powering Up with

CLR High

When the difference between the supply voltages reaches 10 V,

DUTGND

R

R

14k

DAC

Figure 9. Output Stage Powering Up with

CLR High

REV. B