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CD4085BMS Datasheet(PDF) 1 Page - Intersil Corporation |
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CD4085BMS Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 9 page 7-1046 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4085BMS CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate Features • High Voltage Type (20V Rating) • Medium Speed Operation - tPHL = 90ns - tPLH = 125ns (Typ.) at 10V • Individual Inhibit Controls • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline pack- ages: Braze Seal DIP H4H Frit Seal DIP H1B Ceramic Flatpack H5W December 1992 File Number 3327 Pinout CD4085BMS TOP VIEW Functional Diagram A1 B1 E1 = INHI + A1B1 + C1D1 E2 = INH2 + A2B2 + C2D2 A2 B2 VSS VDD D1 C1 INHIBIT 2 INHIBIT 1 D2 C2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD = 14 VSS = 7 INHIBIT 1 A1 B1 C1 D1 10 1 2 12 13 3 E1 INHIBIT 2 A2 B2 C2 D2 11 5 6 8 9 4 E2 E = INHIBIT + AB + CD LOGIC 1 = HIGH LOGIC 0 = LOW |
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