CD54AC02F3A datasheet(4/4 Pages) INTERSIL

Part #	CD54AC02F3A

Description	Quad 2-Input NOR Gate

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Manufacturer	INTERSIL [Intersil Corporation]

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Switching Speciﬁcations Input tr, tf = 3ns, CL = 50pF (Worst Case)

PARAMETER

SYMBOL

VCC (V)

-55oC TO 125oC

UNITS

MIN

TYP

MAX

AC TYPES

Propagation Delay, Input to Output

tPLH, tPHL

1.5

-

144

ns

3.3 (Note 9)

3

-

20.1

ns

5 (Note 10)

2

-

11.5 (Note 8)

ns

Input Capacitance

CI

--

-

10

pF

Power Dissipation Capacitance

CPD (Note 11)

-

55

-

pF

ACT TYPES

Propagation Delay, Input to Output

tPLH

tPHL

5 (Note 10)

2.1

-

12.2 (Note 8)

ns

Input Capacitance

CI

--

-

10

pF

Power Dissipation Capacitance

CPD (Note 11)

-

55

-

pF

NOTES:

8. Limits tested at 100%.

9. 3.3V Min at 3.6V, Max at 3V.

10. 5V Min at 5.5V, Max at 4.5V

11. CPD is used to determine the dynamic power consumption per gate.

AC: PD = VCC

2 f

i (CPD + CL)

ACT: PD = VCC

2 f

i (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test)

DC

DC BURN-IN I

DC BURN-IN II

OPEN

GROUND

VCC (6V)

OPEN

GROUND

VCC (6V)

CD54AC/ACT02

1, 4, 10, 13

2, 3, 5-9, 11,12

14

1, 4, 10, 13

7

2, 3, 5, 6, 8, 9, 11,

12, 14

AC

OPEN

GROUND

1/2 VCC (3V)

VCC (6V)

OSCILLATOR

50kHz

25kHz

CD54AC/ACT02

-

7

1, 4, 10, 13

14

2, 3, 5, 6, 8, 9, 11,

12

-

NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ.

FIGURE 1. PROPAGATION DELAY TIMES

tr = 3ns

tf = 3ns

90%

VS

10%

GND

INPUT

tPHL

tPLH

VS

LEVEL

VI

VO

DUT

OUTPUT

RL (NOTE)

OUTPUT

LOAD

500

Ω

CL

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 2. PROPAGATION DELAY TIMES

CD54AC

CD54ACT

Input Level

VCC

3V

Input Switching Voltage, VS

0.5 VCC

1.5V

Output Switching Voltage, VS

0.5 VCC

CD54AC02F3A, CD54ACT02F3A

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CD54AC02F3A Datasheet(PDF) 4 Page - Intersil Corporation

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