AD7946_15 datasheet(5/24 Pages) AD

Part #	AD7946

Description	14-Bit, 500 kSPS, PulSAR ADC in MSOP and LFCSP

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Data Sheet

AD7946

TIMING SPECIFICATIONS

TA = −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

See Figure 2 and Figure 3 for load conditions.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

tCONV

0.5

1.6

µs

Acquisition Time

tACQ

400

ns

Time Between Conversions

tCYC

2

µs

CNV Pulse Width (CS Mode)

tCNVH

10

ns

SCK Period (CS Mode)

tSCK

15

ns

SCK Period (Chain Mode)

tSCK

VIO Above 4.5 V

17

ns

VIO Above 3 V

18

ns

VIO Above 2.7 V

19

ns

VIO Above 2.3 V

20

ns

SCK Low Time

tSCKL

7

ns

SCK High Time

tSCKH

7

ns

SCK Falling Edge to Data Remains Valid

tHSDO

5

ns

SCK Falling Edge to Data Valid Delay

tDSDO

VIO Above 4.5 V

14

ns

VIO Above 3 V

15

ns

VIO Above 2.7 V

16

ns

VIO Above 2.3 V

17

ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

tEN

VIO Above 4.5 V

15

ns

VIO Above 2.7 V

18

ns

VIO Above 2.3 V

22

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

tDIS

25

ns

SDI Valid Setup Time from CNV Rising Edge (CS Mode)

tSSDICNV

15

ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

tHSDICNV

0

ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

tSSCKCNV

5

ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

tHSCKCNV

5

ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

tSSDISCK

3

ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

tHSDISCK

4

ns

SDI High to SDO High (Chain Mode with Busy Indicator)

tDSDOSDI

VIO Above 4.5 V

15

ns

VIO Above 2.3 V

26

ns

Rev. B | Page 5 of 24

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