Data Sheet

AD8324

Rev. B | Page 7 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. 20-Lead LFCSP Pin Configuration

Figure 6. 20-Lead QSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

20-Lead

LFCSP

20-Lead

QSOP

Mnemonic

Description

1, 2, 5, 9,

18, 19

1, 3, 4, 7,

11, 20

GND

Common External Ground Reference.

3

5

4

6

6

8

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0

to Logic 1 transition transfers the latched data to the attenuator core (updates the gain) and

simultaneously inhibits serial data transfer into the register. A Logic 1 to Logic 0 transition inhibits

the data latch (holds the previous and simultaneously enables the register for serial data load).

7

9

SDATA

Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal

register with the most significant bit (MSB) first.

8

10

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave shift register. Logic 0 to Logic 1 transition latches the data bit, and a Logic 1 to Logic 0

transfers the data bit to the slave. This requires the input serial data-word to be valid at or before

this clock transition.

10

12

SLEEP

Low Power Sleep Mode. In sleep mode, the supply current of the AD8324 is reduced to 30 μA. A

11

13

NC

No Connect. Do not connect to this pin.

12

14

BYP

Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor).

13

15

14

16

15

17

RAMP

External RAMP Capacitor (Optional).

16

18

TXEN

Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission.

17, 20

2, 19

Common Positive External Supply Voltage.

0

Not

applicable

EPAD

Exposed Pad. The exposed pad must be connected to a solid copper plane with low thermal

resistance. This applies to the 20-lead LFCSP package only.

TOP VIEW

(Not to Scale)

AD8324

1

2

3

4

5

15

14

13

12

11

16

17

20 19 18

67

8

9

10

GND

GND

GND

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO A SOLID COPPER PLANE

WITH A LOW THERMAL RESISTANCE. THIS APPLIES TO THE 20-LEAD

LFCSP PACKAGE ONLY.

RAMP

BYP

NC

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD8324

TXEN

SDATA

CLK

SLEEP

BYP

NC

NC = NO CONNECT

GND

GND

GND

GND

GND

RAMP

GND

DATEN