AD9430_15 datasheet(8/44 Pages) AD

Part #	AD9430

Description	12-Bit, 170/210 MSPS 3.3 V A/D Converter

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Manufacturer	AD [Analog Devices]

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AD9430

Rev. E | Page 8 of 44

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.

Table 4.

Test

AD9430-170

AD9430-210

Parameter (Conditions)

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

Maximum Conversion Rate1

Full

VI

170

210

MSPS

Minimum Conversion Rate1

Full

V

40

MSPS

CLK+ Pulse Width High (tEH)1

Full

IV

2

12.5

2

12.5

ns

CLK+ Pulse Width Low (tEL)1

Full

IV

2

12.5

2

12.5

ns

DS Input Setup Time (tSDS)2

Full

IV

–0.5

ns

DS Input Hold Time (tHDS)2

Full

IV

1.75

ns

OUTPUT (CMOS Mode)

Valid Time (tV)

Full

IV

2

ns

Propagation Delay (tPD)

Full

IV

3.8

5

3.8

5

ns

Rise Time (tR) (20% to 80%)

25°C

V

1

ns

Fall Time (tF) (20% to 80%)

25°C

V

1

ns

DCO Propagation Delay (tCPD)

Full

IV

3.8

5

3.8

5

ns

Data to DCO Skew (tPD to tCPD)

Full

IV

–0.5

0

+0.5

–0.5

0

+0.5

ns

Interleaved Mode (A, B Latency)

Full

IV

14, 14

Cycles

Parallel Mode (A, B Latency)

Full

IV

15, 14

Cycles

OUTPUT (LVDS Mode)

Valid Time (tV)

Full

VI

2.0

ns

Propagation Delay (tPD)

Full

VI

3.2

4.3

3.2

4.3

ns

Rise Time (tR) (20% to 80%)

25°C

V

0.5

ns

Fall Time (tF) (20% to 80%)

25°C

V

0.5

ns

DCO Propagation Delay (tCPD)

Full

VI

1.8

2.7

3.8

1.8

2.7

3.8

ns

Data to DCO Skew (tPD – tCPD)

Full

IV

0.2

0.5

0.8

0.2

0.5

0.8

ns

Latency

Full

IV

14

Cycles

APERTURE DELAY (tA)

25°C

V

1.2

ns

APERTURE UNCERTAINTY (Jitter, tJ)

25°C

V

0.25

ps rms

OUT OF RANGE RECOVERY TIME (CMOS and LVDS)

25°C

V

1

Cycles

1 All ac specifications tested by differentially driving CLK+ and CLK−.

2 DS inputs used in CMOS mode only.

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