AD9461

Rev. 0 | Page 10 of 28

74

D4+

73

D3+

72

D2+

69

DNC

70

D0+ (LSB)

71

D1+

75

DRGND

68

DCO+

67

DCO–

66

DNC

64

DRVDD

63

DRGND

62

DNC

61

DNC

60

DNC

59

DNC

58

DNC

57

DNC

56

DNC

55

DNC

54

DNC

53

DNC

52

DNC

51

DNC

65

DNC

PIN 1

DNC = DO NOT CONNECT

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

2

DNC

3

OUTPUT MODE

4

DFS

7

SENSE

6

AVDD1

5

LVDS_BIAS

1

DCS MODE

8

VREF

9

AGND

10

REFT

12

AVDD2

13

AVDD2

14

AVDD2

15

AVDD2

16

AVDD2

17

AVDD2

18

AVDD1

19

AVDD1

20

AVDD1

21

AGND

22

VIN+

23

VIN–

24

AGND

25

AVDD2

11

REFB

AD9461

CMOS MODE

TOP VIEW

(Not to Scale)

Figure 5. 100-Lead TQFP_EP, Pin Configuration in CMOS Mode

Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode

Pin No.

Mnemonic

Description

1

DCS MODE

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.

DCS = low (AGND) to enable DCS (recommended).

DCS = high (AVDD1) to disable DCS.

2, 49 to 62, 65 to 66, 69

DNC

Do Not Connect. These pins should float.

3

OUTPUT MODE

CMOS-Compatible Output Logic Mode Control Pin.

OUTPUT MODE = 0 for CMOS mode.

OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

4

DFS

Data Format Select Pin. CMOS control pin that determines the format of the output data.

DFS = high (AVDD1) for twos complement.

DFS = low (ground) for offset binary format.

5

LVDS_BIAS

Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.

6, 18 to 20, 32 to 34, 36,

38, 43 to 45, 92 to 97

AVDD1

3.3 V (±5%) Analog Supply.

7

SENSE

Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog

input range); connect to AVDD1 for external reference.

8

VREF

1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming

resistors. Decouple to ground with 0.1 μF and 10 μF capacitors.

9, 21, 24, 39, 42, 46, 91, 98,

99, Exposed Heat Sink

AGND

Analog Ground. The exposed heat sink on the bottom of the package must be connected to

AGND.

10

REFT

Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB

(Pin 11) with 0.1 μF and 10 μF capacitors.