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AD9661A Datasheet(PDF) 7 Page - Analog Devices

Part # AD9661A
Description  Laser Diode Driver with Light Power Control
Download  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9661A Datasheet(HTML) 7 Page - Analog Devices

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AD9661A
REV. 0
–7–
TIME CONSTANTS –
100
30
0
05
1
24
20
10
3
40
50
60
70
80
90
Figure 4. Calibration Time
Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9661A drives the
hold capacitor to
≈V
REF. In this case, or in any case where the
output current is more than 10% out of calibration, R will range
from 300
Ω to 550 Ω for the model above; the higher value should
be used for calculating the worst case calibration time. Following
the example above, if CHOLD were chosen as 4.5 nF, then
τ = RC = 550 Ω × 4.5 nF would be 2.48 µs. For an initial
calibration error < 1%, the initial calibration time should be
> 5
τ = 12.36 µs.
Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T/H decreases as the hold voltage approaches its
final value.
Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (< 10%), the
resistance for the model above will be in the range of 75
Ω to
140
Ω. Again, the higher value should be used to estimate the
worst case time needed for recalibration.
Continuing with the example above, since the droop error dur-
ing hold time is < 5%, we meet the criteria for recalibration and
τ = RC = 140 Ω × 4.5 nF = 0.64 µs. To get a final error of 1%
after recalibration, the 5% droop must be corrected to within a
20% error (20%
× 5% = 1%). A 2 τ recalibration time of 1.2 µs
is sufficient.
Continuous Recalibration
In applications where the hold capacitor is small (< 500 pF) and
the WRITE PULSE signals always have a pulse width > 25 ns,
the user may continuously calibrate the feedback loop. In such
an application, the
CAL signal should be held logic LOW, and
the PULSE signal will control loop calibration via the internal
AND gate. In such application, it is important to optimize the
layout for the TZA (POWER MONITOR, GAIN, RGAIN and
CGAIN).
Driving the Analog Inputs
The POWER LEVEL input of the AD9661A drives the track
and hold amplifier and allows the user to adjust the amount of
output current as described above. The input voltage range is
VREF to VREF + 1.6 V, requiring the user to create an offset of
VREF for a ground based signal (see below for description of the
on board level shift circuit). The circuit below will perform the
level shift and scale the output of a DAC whose output is from
ground to a positive voltage. This solution is especially attrac-
tive because both the DAC and the op amp can run off a single
+5 V supply, and the op amp doesn’t have to swing rail to rail.
DAC
V
DAC
OP191
+5V
V
REF + VDAC
= V
POWER LEVEL
R2
R1
BIAS LEVEL
V
REF
AD9661A
R1
R1
R2
R2
Figure 5. Driving the Analog Inputs
Using the Level Shift Circuit
The AD9661A includes an on board level shift circuit to provide
the offset described above. The input, LEVEL SHIFT IN, has
an input range from 0.1 V to 1.6 V. The output, LEVEL
SHIFT OUT, has a range from VREF to VREF +1.6 V, and can
drive POWER MONITOR. The linearity of the level shift cir-
cuit is poor for inputs below 100 mV. Between 100 mV and
1.6 V it is about 7 bits accurate.
Layout Considerations
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as
possible, and isolated from digital signals to avoid coupling in
noise. In particular, digital lines should be isolated from
OUTPUT, SENSE IN, POWER LEVEL, LEVEL SHIFT IN
POWER MONITOR, and HOLD traces. Digital signal paths
should also be kept short, and run lengths matched to avoid
propagation delay mismatch.
Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1
µF
surface mount capacitors, placed as close as possible to the
AD9661A +VS connections, and the +VS connection to the laser
diode meet this requirement. Multilayer circuit boards allow
designers to lay out signal traces without interrupting the ground
plane, and provide low impedance power planes to further
reduce noise.


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