REV. B

AD9731

–9–

THEORY AND APPLICATIONS

The AD9731 high speed digital-to-analog converter utilizes

most significant bit decoding and segmentation techniques to

reduce glitch impulse and deliver high dynamic performance

on lower power consumption than previous bipolar DAC

technologies.

The design is based on four main subsections: the decoder/

driver circuits, the edge-triggered data register, the switch net-

work, and the control amplifier. An internal band gap reference

is included to allow operation of the device with minimum

external support components.

Digital Inputs/Timing

The AD9731 has TTL/high speed CMOS-compatible single-ended

inputs for data inputs and clock. The switching threshold is 1.5 V.

In the decoder/driver section, the three MSBs are decoded to

seven “thermometer code” lines. An equalizing delay is included

for the seven least significant bits and the clock signals. This

delay minimizes data skew and data setup and hold times at the

register inputs.

The on-board register is rising edge triggered and should be

used to synchronize data to the current switches by applying a

pulse with proper data setup and hold times as shown in the

timing diagram. Although the AD9731 is designed to provide

isolation of the digital inputs to the analog output, some cou-

pling of digital transitions is inevitable. Digital feedthrough can

be minimized by forming a low pass filter at the digital input by

using a resistor in series with the capacitance of each digital

input. This common high speed DAC application technique has

the effect of isolating digital input noise from the analog output.

Input Clock and Data Timing Relationship

SINAD in a DAC is dependent on the relationship between the

position of the clock edges and the point in time at which the

input data changes. The AD9731 is rising edge triggered, and so

exhibits SINAD sensitivity when the data transition is close to

this edge. In general, the goal when applying the AD9731 is to

make the data transition close to the falling clock edge. This

becomes more important as the sample rate increases. Figure 2

shows the relationship of SINAD to clock placement from the

AD9731 and a competitive part, both sampling at 125 MSPS.

The AD9731 has excellent performance as far as the narrowness

of the “window” in which it is sensitive to SINAD.

TIME OF DATA PLACEMENT RELATIVE TO

RISING EDGE OF CLOCK – ns

60

–4

50

40

30

20

10

0

–3

–2

–1

0

1

2

3

4

COMPETITION

AD9731

References

The internal band gap reference, control amplifier, and refer-

ence input are pinned out to provide maximum user flexibility

in configuring the reference circuitry for the AD9731. When

using the internal reference, REF OUT (Pin 25) should be con-

nected to CONTROL AMP IN (Pin 26). CONTROL AMP OUT

(Pin 24) should be connected to REF IN (Pin 23). A 0.1

mF

improves settling time by decoupling switching noise from the

current sink baseline. A reference current cell provides feedback

Full-scale current is determined by CONTROL AMP IN and

The internal reference is nominally –1.25 V with a tolerance of

±8% and typical drift over temperature of 100 ppm/∞C. If

greater accuracy or temperature stability is required, an external

reference can be used. The AD589 reference features 10 ppm/

∞C

drift over the 0

∞C to 70∞C temperature range.

Two modes of multiplying operation are possible with the

AD9731. Signals with bandwidths up to 2.5 MHz and input

swings from –0.6 V to –1.2 V can be applied to the CONTROL

AMP IN pin as shown in Figure 3. Because the control ampli-

fier is internally compensated, the 0.1

mF capacitor discussed

above can be reduced to maximize the multiplying bandwidth.

However, it should be noted that output settling time, for

changes in the digital word, will be degraded.

–0.6 TO –1.2V

2.5MHz TYPICAL

0.1 F

CONTROL

AMP IN

CONTROL

AMP OUT

REFERENCE IN

AD9731

Figure 3. Low Frequency Multiplying Circuit