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HCTS393DMSR Datasheet(PDF) 1 Page - Intersil Corporation

Part # HCTS393DMSR
Description  Radiation Hardened Dual 4-Stage Binary Counter
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HCTS393DMSR Datasheet(HTML) 1 Page - Intersil Corporation

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS393DMSR
-55oC to +125oC
Intersil Class S Equivalent
14 Lead SBDIP
HCTS393KMSR
-55oC to +125oC
Intersil Class S Equivalent
14 Lead Ceramic Flatpack
HCTS393D/Sample
+25oC
Sample
14 Lead SBDIP
HCTS393K/Sample
+25oC
Sample
14 Lead Ceramic Flatpack
HCTS393HMSR
+25oC
Die
Die
HCTS393MS
Radiation Hardened
Dual 4-Stage Binary Counter
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
CP 1
MR 1
Q0 1
Q1 1
Q2 1
Q3 1
GND
VCC
2 CP
2 MR
2 Q0
2 Q1
2 Q2
2 Q3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
CP 1
MR 1
Q0 1
Q1 1
Q2 1
Q3 1
GND
VCC
2 CP
2 MR
2 Q0
2 Q1
2 Q2
2 Q3
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Standard Outputs: 10 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii
≤ 5µA at VOL, VOH
Description
The Intersil HCTS393MS is a Radiation Hardened 4-stage
riple-carry binary counter. All counter stages are master-
slave flip-flop. The state of the stage advances one count on
the negative transition of each clock pulse. A high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
The HCTS393MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS393MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
August 1995
Spec Number
518633
File Number
3071.1


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