Electronic Components Datasheet Search |
|
AD9876 Datasheet(PDF) 3 Page - Analog Devices |
|
AD9876 Datasheet(HTML) 3 Page - Analog Devices |
3 / 24 page REV. A –3– AD9876 Test Parameter Temp Level Min Typ Max Unit Rx PATH GAIN/OFFSET Minimum Programmable Gain 25 °C III –6 dB Maximum Programmable Gain (12 MHz Filter) 25 °C III 36 dB Maximum Programmable Gain (26 MHz Filter) 25 °C III 30 dB Gain Step Size 25 °C III 2 dB Gain Step Accuracy 25 °C III ±0.4 dB Gain Range Error 25 °C III ±1.0 dB Offset Error, PGA Gain = 0 dB 25 °C III ±10 LSB Absolute Gain Error 25 °C III ±0.8 dB Rx PATH INPUT CHARACTERISTICS Input Voltage Range Full III 4 Vppd Input Capacitance 25 °C III 4 pF Differential Input Resistance 25 °C III 270 Ω Input Bandwidth (–3 dB) 25 °C III 50 MHz Input Referred Noise (at –36 dB Gain with Filter) 25 °C III 16 µV rms Input Referred Noise (at –6 dB Gain with Filter) 25 °C III 684 µV rms Common-Mode Rejection 25 °C III 40 dB Rx PATH LPF (Low Cutoff Frequency) Cutoff Frequency 25 °C III 12 MHz Cutoff Frequency Variation 25 °C III ±7% Attenuation @ 22 MHz 25 °C III 20 dB Pass-Band Ripple 25 °C III ±1.0 dB Group Delay Variation 25 °C III 30 ns Settling Time (to 1% FS, Min to Max Gain Change) 25 °C III 150 ns Total Harmonic Distortion at Max Gain (THD) 25 °C III –68 dBc Rx PATH LPF (High Cutoff Frequency) Cutoff Frequency 25 °C III 26 MHz Cutoff Frequency Variation 25 °C III ±7% Attenuation @ 44 MHz 25 °C III 20 dB Pass-Band Ripple 25 °C III ±1.2 dB Group Delay Variation 25 °C III 15 ns Settling Time (to 1% FS, Min to Max Gain Change) 25 °C III 80 ns Total Harmonic Distortion at Max Gain (THD) 25 °C III –65 dBc Rx PATH DIGITAL HPF Latency (ADC Clock Source Cycles) Full II 1 Cycle Roll-Off in Stop Band Full II 6 dB/Octave –3 dB Frequency Full II fADC /400 Hz Rx PATH DISTORTION PERFORMANCE IMD: f1 = 6.5 MHz, f2 = 7.7 MHz 12 MHz Filter : 0 dB Gain 25 °C III –65 dBc : 30 dB Gain 25 °C III –57 dBc 26 MHz Filter : 0 dB Gain 25 °C III –65 dBc : 30 dB Gain 25 °C III –56 dBc POWER-DOWN/DISABLE TIMING DAC IOUT OFF after Tx QUIET Asserted Full II 200 ns DAC IOUT ON after Tx QUIET De-Asserted Full II 1 µs Power-Down Delay (Active to Power-Down) DAC Full II 400 ns Interpolator Full II 200 ns Power-Up Delay (Power-Down to Active) DAC Full II 40 µs PLL Full II 10 µs ADC Full II 1000 µs PGA Full II 1 µs LPF Full II 1 µs Interpolator Full II 200 ns VRC Full II 2 µs Minimum RESET Pulsewidth Low (tRL) Full II 5 fOSCIN Cycles |
Similar Part No. - AD9876_15 |
|
Similar Description - AD9876_15 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |