AD9995_15 datasheet(9/60 Pages) AD

Part #	AD9995

Description	12-Bit CCD Signal Processor with Precision Timing Generator

Download	60 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

Logo

9 / 60 page

AD9995

–9–

SYSTEM OVERVIEW

Figure 1 shows the typical system block diagram for the AD9995

used in Master mode. The CCD output is processed by the

AD9995’s AFE circuitry, which consists of a CDS, VGA, black

level clamp, and A/D converter. The digitized pixel information

is sent to the digital image processor chip, which performs the

postprocessing and compression. To operate the CCD, all CCD

timing parameters are programmed into the AD9995 from the

system microprocessor through the 3-wire serial interface. From

the system master clock, CLI, provided by the image processor

or external crystal, the AD9995 generates all of the CCD’s hori-

zontal and vertical clocks and all internal AFE clocks. External

synchronization is provided by a SYNC pulse from the micropro-

cessor, which will reset internal counters and resync the VD and

HD outputs.

Alternatively, the AD9995 may be operated in Slave mode, in

which VD and HD are provided externally from the image pro-

cessor. In this mode, all AD9995 timing will be synchronized

with VD and HD.

CCDIN

MSHUT

STROBE

H1–H4, RG, VSUB

V1–V6, VSG1–VSG5, SUBCK

CCD

V-DRIVER

AD9995

AFETG

DIGITAL

IMAGE

PROCESSING

ASIC

DOUT

DCLK

HD, VD

CLI

SERIAL

INTERFACE

SYNC

The H-drivers for H1–H4 and RG are included in the AD9995,

allowing these clocks to be directly connected to the CCD.

H-drive voltage of up to 3.3 V is supported. An external V-driver

is required for the vertical transfer clocks, the sensor gate pulses,

and the substrate clock.

The AD9995 also includes programmable MSHUT and

STROBE outputs, which may be used to trigger mechanical

shutter and strobe (flash) circuitry.

Figures 2 and 3 show the maximum horizontal and vertical

counter dimensions for the AD9995. All internal horizontal and

vertical clocking is controlled by these counters to specify line

and pixel locations. Maximum HD length is 4095 pixels per line,

and maximum VD length is 4095 lines per field.

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

MAXIMUM

FIELD

DIMENSIONS

Figure 2. Vertical and Horizontal Counters

VD

HD

MAX VD LENGTH IS 4095 LINES

CLI

MAX HD LENGTH IS 4095 PIXELS

Figure 3. Maximum VD/HD Dimensions

REV. 0

Similar Part No. - AD9995_15

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD9995KCP	1Mb / 60P	12-Bit CCD Signal Processor with Precision Timing ??Generator REV. 0
Analog Devices	AD9995KCPRL	1Mb / 60P	12-Bit CCD Signal Processor with Precision Timing ??Generator REV. 0

More results

Similar Description - AD9995_15

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD9992	775Kb / 92P	12-Bit CCD Signal Processor with Precision Timing Generator REV. C
	AD9992	1Mb / 92P	12-Bit CCD Signal Processor with Precision Timing Generator Rev. C
	AD9995	1Mb / 60P	12-Bit CCD Signal Processor with Precision Timing ??Generator REV. 0
	AD9994	63Kb / 2P	12-Bit CCD Signal Processor with Precision Timing Generator Rev. Sp0
	AD9992	1Mb / 92P	12-Bit CCD Signal Processor with Precision Timing Generator REV. C
	AD9992	1Mb / 92P	12-Bit CCD Signal Processor with Precision Timing Generator REV. C
	AD9971	67Kb / 2P	12-Bit CCD Signal Processor with Precision Timing Rev. SpA
	AD9971	79Kb / 2P	12-Bit CCD Signal Processor with Precision Timing Rev. SpB
	AD9937	416Kb / 44P	CCD Signal Processor with Precision Timing Generator REV. 0
	AD9929	564Kb / 64P	CCD Signal Processor with Precision Timing Generator REV. A

More results

AD9995 Datasheet(PDF) 9 Page - Analog Devices

AD9995 Datasheet(HTML) 9 Page - Analog Devices

Similar Part No. - AD9995_15

Similar Description - AD9995_15

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL