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AD73422 Datasheet(PDF) 4 Page - Analog Devices |
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AD73422 Datasheet(HTML) 4 Page - Analog Devices |
4 / 36 page REV. 0 –4– AD73422–SPECIFICATIONS Parameter Test Conditions Min Typ Max Units DSP SECTION VIH Hi-Level Input Voltage 1, 2 @ VDD = max 2.0 V VIH Hi-Level CLKIN Voltage @ VDD = max 2.2 V VIL Lo-Level Input Voltage 1, 3 @ VDD = min 0.8 V VOH Hi-Level Output Voltage 1, 4, 5 @ VDD = min IOH = –0.5 mA 2.4 V @ VDD = min IOH = –100 µA6 VDD – 0.3 V VOL Lo-Level Output Voltage 1, 4, 5 @ VDD = min IOL = 2 mA 0.4 V IIH Hi-Level Input Current 3 @ VDD = max VIN = VDD max 10 µA IIL Lo-Level Input Current 3 @ VDD = max VIN = 0 V 10 µA IOZH Three-State Leakage Current 7 @ VDD = max VIN = VDD max 8 10 µA IOZL Three-State Leakage Current 7 @ VDD = max VIN = 0 V 8 10 µA IDD Supply Current (Idle) 9 @ VDD = 3.6 tCK = 19 ns 10 12 mA tCK = 25 ns 10 10 mA tCK = 30 ns 10 9mA IDD Supply Current (Dynamic) 11 @ VDD = 3.6 TAMB = +25 °C tCK = 19 ns 10 54 mA tCK = 25 ns 10 43 mA tCK = 30 ns 10 37 mA CI Input Pin Capacitance 3, 6, 12 @ VIN = 2.5 V fIN = 1.0 MHz TAMB = +25 °C8 12 pF CO Output Pin Capacitance 6, 7, 12, 13 @ VIN = 2.5 V fIN = 1.0 MHz TAMB = +25 °C 1020pF NOTES 1 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH. 5 Although specified for TTL outputs, all AD73422 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7. 8 0 V on BR. 9 Idle refers to AD73422 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. 10 V IN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 11 I DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 Applies to PBGA package type. 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. (AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.) |
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Similar Description - AD73422_15 |
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